Dominant Layer for Stress-Induced Positive Charges in Hf-Based Gate Stacks

Abstract

Positive charges in Hf-based gate stacks play an important role in the negative bias temperature instability of pMOSFETs, and their suppression is a pressing issue. The location of positive charges is not clear, and central to this letter is determining which layer of the stack dominates positive charging. The results clearly show that positive charges are dominated by the interfacial layer (IL) and that they do not pile up at the HfSiON/IL interface. The results support the assumption that positive charges are located close to the IL/substrate interface. Unlike electron trapping that reduces rapidly for thinner Hf dielectric layer, positive charges cannot be reduced by using a thinner HfSiON film.

Full text

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IEEE ELECTRON DEVICE LETTERS1
Dominant Layer for Stress-Induced Positive Charges
in Hf-Based Gate Stacks
Jian F. Zhang, Mo Huai Chang, Zhigang Ji, Lin Lin, Isabelle Ferain, Guido Groeseneken,
Luigi Pantisano, Stefan De Gendt, and Marc M. Heyns
Abstract—Positive charges in Hf-based gate stacks play an
important role in the negative bias temperature instability of
pMOSFETs, and their suppression is a pressing issue. The loca-
tion of positive charges is not clear, and central to this letter is
determining which layer of the stack dominates positive charging.
Theresultsclearlyshowthatpositivechargesaredominatedbythe
interfacial layer (IL) and that they do not pile up at the HfSiON/IL
interface. The results support the assumption that positive charges
are located close to the IL/substrate interface. Unlike electron
trapping that reduces rapidly for thinner Hf dielectric layer, posi-
tive charges cannot be reduced by using a thinner HfSiON film.
Index Terms—Hf silicates, high-k gate dielectric, instability,
negative bias temperature instability (NBTI), positive charges,
reliability, spatial distribution.
I. INTRODUCTION
T
comparison with SiON, Hf-based stacks generally suffer from
higher instabilities [1]–[8]. Positive charging causes negative
bias temperature instability (NBTI) and limits the lifetime of
pMOSFETs, and there is a pressing need for suppressing it.
At present, there is little information available on which layer
of the stack dominates positive charging, and finding it is
the objective of this letter. Considering that the quality of
Hf oxides and silicates is generally inferior to that of SiON,
one may expect that there are more defects in Hf dielectric
layers than in interfacial layer (IL) and that the charging can
be reduced by using thinner Hf dielectric layers. Early works
[5], [6] show that this is indeed the case for as-grown electron
traps. However, we will show that positive charges are dom-
inated by the IL and that reducing the HfSiON thickness has
little effect on positive charging.
O CONTROL gate leakage, Hf-based dielectric stack has
been selected to replace SiON as a gate insulator. In
Manuscript received August 21, 2008; revised September 9, 2008. Current
version published November 21, 2008. This work was supported by the
Engineering and Physical Science Research Council of U.K. under Grant
EP/C003071/1. The review of this letter was arranged by Editor C.-P. Chang.
J. F. Zhang, M. H. Chang, Z. Ji, and L. Lin are with the School of Engi-
neering, Liverpool John Moores University, L3 3AF Liverpool, U.K. (e-mail:
J.F.Zhang@ljmu.ac.uk; m.h.chang@ljmu.ac.uk; z.ji@2006.ljmu.ac.uk; l.lin@
2005.ljmu.ac.uk).
I.FerainandL.PantisanoarewiththeIMEC,3001Leuven,Belgium(e-mail:
Ferain@imec.be; Luigi.Pantisano@imec.be).
G. Groeseneken, S. De Gendt, and M. M. Heyns are with the IMEC,
3001 Leuven, Belgium, and also with the Katholieke Universiteit Leuven,
3001 Leuven, Belgium (e-mail: guido.groeseneken@imec.be; stefan.degendt@
imec.be; heyns@imec.be).
Digital Object Identifier 10.1109/LED.2008.2006288
II. DEVICES AND EXPERIMENTS
Hf silicates (80% Hf) were prepared by atomic layer de-
position to a thickness of 1, 2, and 3 nm on three IMEC-
cleaned wafers. The IL is 1 nm, and the gate is TiN. Both the
channel length and width are 1 μm. A slant-etched wafer is also
used, with HfSiON fixed at 2 nm and the IL thickness varying
between 1.7 and 3.6 nm across the wafer.
The threshold voltage shift ΔVth, was measured by extrap-
olation with a drain bias of −0.1 V [9]. Both quasi-dc [10]
and pulse Id∼ Vg [11], [12] were used with a measurement
time of 6 s and 5 μs, respectively. The ΔVth has two com-
ponents, namely, a contribution from generated interface states
ΔVth(ΔDit), and a contribution from positive charges in di-
electric ΔVth(ΔNot) so that
ΔVth= ΔVth(ΔDit) + ΔVth(ΔNot).
Early works [13], [14] reported that the generated interface
states are acceptor-type above the midgap of Si and donor-type
below the midgap. As a result, ΔVth(ΔNot) can be determined
from the shift of the gate voltage at the midgap of Si, where
the net charge of interface states is negligible. The density of
generated interface states was measured from the change in the
subthreshold swing [15] and charge pumping (CP).
III. RESULTS AND DISCUSSIONS
To determine the dominant layer for positive charges, three
samples with different thicknesses of HfSiON layers were used.
The problem is that positive charges increase with the stress
level and that a comparison of different samples is meaningful
only if they were subjected to the same stress. Under the same
effective oxide field, Fig. 1(a) shows that the difference in
their density of generated interface states ΔDitis negligible,
confirming that they were subjected to the same stress level.
Before assessing the spatial location of ΔNotin Hf-based
stacks, we examine its relative importance to the NBTI-induced
ΔVth. Fig. 1(b) shows a comparison of the contributions of
ΔNot and ΔDit to ΔVth. Initially, ΔDit is negligible, and
ΔVthis dominated by ΔNot, considering that there are preex-
isting defects in the stack [7], [8]. As the stress time increases,
the contribution of ΔDitrises and reaches about one third of
ΔVthfor the last point in Fig. 1(b).
As a first attempt for assessing the spatial distribution of
positive charges, we study the case where they are distributed
throughout the stack. To simplify the analysis, we assume that
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2IEEE ELECTRON DEVICE LETTERS
Fig. 1.
capacitance and where the surface quantization effect has been taken into account. ΔDitmeasured by CP agrees well with that by the subthreshold swing.
(b) Threshold voltage shift ΔVthand its two components, namely, ΔVth(ΔNot) and ΔVth(ΔDit).
(a) Density of created interface states ΔDitunder Eox= −11 MV/cm. Eox= (Vg− Vfb− Φs)/EOT, where EOT was extracted from the inversion
Fig. 2.
assumptions: 1) ρHF= ρIF(indicated by dashed lines); 2 ) ρIF= 0 (indicated by dotted lines); and 3) ρHF= 0 (indicated by solid lines). (b) Prediction is under
the following two assumptions for positive charges: 1) at the HfSiON/IL interface (indicated by dashed lines); and 2) at the IL/substrate interface (indicated by
solid lines). Quasi-dc measurement time is 6 s.
Comparison of (symbols) test data with the (lines) prediction based on (a) volume and (b) sheet distributions. (a) Prediction is under the following three
the volume density ρ in both HfSiON and the IL is constant.
Although this will not give a detailed spatial distribution, it will
allow for the assessment of which layer dominates the positive
charges. ΔVth(ΔNot) is related to ρ by
ΔVth(ΔNot) = −q · ρHF· X2
HF
2 · ε0· kHF
−
q · ρIL
2 · ε0· kIL
·
?
X2
IL+ 2 ·kIL
kHF
· XIL· XHF
?
(1)
where X is the dielectric layer thickness and k is the dielectric
constant (kHF= 16.3). The subscripts “HF” and “IL” repre-
sent HfSiON and IL, respectively. Fig. 2(a) shows a plot the
ΔVth(ΔNot) measured at different stress times for XHF=
1, 2, and 3 nm. At a given time point, we use ΔVth(ΔNot)
at XHF= 3 nm as the base to predict the ΔVth(ΔNot) at
XHF= 1 and 2 nm under three different assumptions.
A. Uniform Distribution With ρHF= ρIL
For each ΔVth(ΔNot) of XHF= 3 nm measured at a given
time, ρHF= ρILcan be calculated from (1). Once ρHF= ρIL
is known, ΔVth(ΔNot) of XHF= 1 and 2 nm at the same time
can be predicted by (1). The results are shown as the two dashed
lines in Fig. 2(a), and the agreement with the test data is poor.
The predicted ΔVth(ΔNot) at XHF= 1 nm is only half of the
measured value.
Fig. 3.
fixed at 2 nm. The solid line is fitted with (3) by assuming that charges pile up
at the substrate interface.
Effects of IL thickness XIFon ΔVth(ΔNot). The HfSiON layer is
B. All Charges in HfSION and ρIL= 0
The predicted ΔVth(ΔNot) is represented by the two dotted
lines, and they depart further from the test data. The predicted
ΔVth(ΔNot) at XHF= 1 nm is only 15% of the test data so
that we can rule out that positive charges are dominated by the
bulk of HfSiON.
C. All Charges in the IL and ρHF= 0
The predicted ΔVth(ΔNot) is represented by the two solid
lines, and they are closest to the test data among the three
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ZHANG et al.: DOMINANT LAYER FOR STRESS-INDUCED POSITIVE CHARGES IN Hf-BASED GATE STACKS3
Fig. 4.
in Fig. 2; here, however, the pulsed measurement was used with a measurement time of 5 μs.
Comparison of the prediction with the test data based on (a) volume and (b) sheet distributions. The symbols and lines have the same meaning as those
assumptions. This supports that the IL dominates the positive
charges. To further improve the agreement between the predic-
tion and test data, we explore the sheet distribution next.
In comparison with conventional MOSFETs with SiON as
the gate dielectric, one new feature for a Hf-based stack is the
presence of a HfSiON/IL interface, and we examine whether
positive charges pile up at this interface. If we assume that all
charges are at the HfSiON/IL interface with an area density of
Q, we have
ΔVth(ΔNot) = −q · XHF· Q
ε0· kHF
.
(2)
The predicted value is shown as the two dashed lines in
Fig. 2(b), and it is less than half of the test data for XHF=
1 nm. Equation (2) also requires ΔVth(ΔNot) to be indepen-
dent of the IL thickness. This is against our test results in Fig. 3
that shows ΔVth(ΔNot) increasing for thicker IL. We conclude
that positive charges are not concentrated at the HfSiON/IL
interface.
AfterrulingouttheHfSiON/ILinterface,itisnaturaltostudy
if positive charges pile up at the IL/Si interface. By assuming
all charges at the substrate interface, we have
ΔVth(ΔNot) = −qQ
?XIL
ε0kIL
+
XHF
ε0kHF
?
.
(3)
The predicted value is shown as the two solid lines in Fig. 2(b),
and a good agreement with the test data is achieved. This
supports that positive charges pile up at the IL/substrate in-
terface and that, consequently, reducing the HfSiON thickness
has little effect on positive charging. The smaller measured
ΔVth(ΔNot) at XHF= 1 nm in Fig. 2(b) results from a larger
gate capacitance when compared with that at XHF= 3 nm. To
explain this pileup, it should be noted that the oxygen vacancy
≡ Si–Si ≡ has been proposed as the main source for positive
charges [16]. It is reasonable to assume that there are more
≡ Si–Si ≡ when moving from a dielectric toward a silicon
substrate. Our data, however, do not give direct information on
the origin or microscopic structure of positive charges.
The results in Fig. 2 were obtained under an electrical field
over the equivalent oxide thickness of Eox= −11 MV/cm
and at 150◦C. The question is whether the dominant layer
is sensitive to the stress conditions. We have checked it with
Eoxin the range between −11 and −18 MV/cm and a tem-
perature between room temperature and 150◦C. Our results
(not shown) confirm that in all stress conditions, the result
is similar to that shown in Fig. 2. To test the impact of the
measurement time, it is reduced from 6 s, in Fig. 2, to 5 μs, in
Fig. 4, by using the pulse Id∼ Vg[11], [12]. Fig. 4 shows that
IL still dominates the positive charges, when the recovery is
suppressed.
IV. CONCLUSION
In this letter, the dominant layer for the stress-induced
positive charge in Hf-based stacks is assessed by varying the
thicknesses of HfSiON and ILs. We conclude that positive
charges in the stack are dominated by the IL. It is ruled out
that positive charges pile up at the HfSiON/IL interface. The
results support that positive charges are located close to the
IL/substrate interface. Consequently, unlike electron trapping, a
reduction of the HfSiON thickness will not reduce the positive
charges.
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