Random-Dopant-Induced Drain Current Variation in Nano-MOSFETs: A Three-Dimensional Self-Consistent Monte Carlo Simulation Study Using “Ab Initio” Ionized Impurity Scattering
A comprehensive simulation study of random-dopant-induced drain current variability is presented for a series of well-scaled n -channel MOSFETs representative of the 90-, 65-, 45-, 35-, and 22-nm technology nodes. Simulations are performed at low and high drain biases using both 3-D drift diffusion (DD) and 3-D Monte Carlo (MC). The ensemble MC simulator incorporates an ldquo ab initio rdquo treatment of ionized impurity scattering through the real-space trajectories of the carriers in the Coulomb potential of the random discrete impurities. When compared with DD simulations, the MC simulations reveal a significant increase in the drain current variability as a result of additional transport variations due to position-dependent Coulomb scattering that is not captured within the DD mobility model. Such transport variations are in addition to the electrostatic variation in carrier density that is alone captured within the DD approach. Through comparison of the DD and MC results, we estimate the relative importance of electrostatic and transport-induced variability at different drain bias conditions.
Available from: E. Moreno
- "The use of MuG MOSFETs could allow the reduction of channel lengths below 14 nm, taking into account the possibility of using undoped channels due to reduced short channel effects (SCEs). Apart from that, a reduced doping leads to lower random impurity effects, such us threshold voltage and the sub-threshold slope dispersion   . "
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ABSTRACT: The scaling of MOSFET transistors makes the use of new device geometries, such as multigate FETs, a need to solve the limitations of the conventional bulk technology. In this context we introduce an analytical model for square Gate All Around (GAA) MOSFETs with rounded corners including quantum effects. The modeling of rounded corners in GAA and FinFET devices is imperative because there are no perfectly square corners in the cross-section of real devices. In this model the 2D inversion charge distribution function (ICDF) is described analytically for devices of different sizes and for different operation regimes. The model reproduces accurately simulated data obtained with a state-of-the-art simulator that solves self-consistently the Poisson and Schrödinger equations in the devices under consideration. The analytical ICDF is used to better understand the device physics and to calculate the inversion charge centroid and the gate-to-channel capacitance for different device geometries and biases for modeling purposes.
Solid-State Electronics 09/2015; 111:180-187. DOI:10.1016/j.sse.2015.06.004 · 1.50 Impact Factor
Available from: Razaidi Hussin
- "In the following, we adopt r c = 0.5 nm as a good compromise between the short-range scattering resolution and numerical efficiency . "
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ABSTRACT: This paper investigates the accuracy and issues of modeling carrier mobility in the channel of a nanoscaled MOSFET in the presence of discrete charges trapped at the channel/oxide interface. By comparing drift-diffusion (DD) and Monte Carlo (MC) simulation results, a quasi-local mobility model accounting for the complex scattering profile associated with a trapped carrier at the center of the channel is firstly derived. The accuracy of this model is evaluated on a test-bed 25-nm MOS transistor at low drain bias condition and for several applied gate biases. The issues in extending this mobility model to high drain biases regime and to the case of randomly positioned trapped charges are then discussed in the second part of this paper. Our findings show that DD simulations can maintain computational efficiency and accuracy at low drain biases, when a proper mobility model is used to describe the impact of discrete trapped charges. On the other hand, more complex corrections, that go beyond the simple mobility modification, are necessary to compensate the different carrier concentrations between DD and MC approaches at high drain biases.
IEEE Transactions on Electron Devices 04/2014; DOI:10.1109/TED.2014.2312820 · 2.47 Impact Factor
Available from: Francisco Gamiz
- "High doping concentrations are required to keep short channel effects under control in nanometric bulk transistors, and therefore, carrier mobility is greatly reduced     . In addition, the random impurity effects in these devices are by no means negligible since they produce a considerable dispersion of fundamental parameters such as the threshold voltage and the sub-threshold slope . In this context, new structures have been proposed to overcome these limitations. "
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ABSTRACT: A comprehensive study of Coulomb and surface-roughness scattering mechanisms in double-gate MOSFETs is presented. It was considered that the approach followed would facilitate the development of mobility models to be incorporated in compact models of these devices. Mobility curves for structures with different interfacial charges and roughness characteristics at the oxide–semiconductor interfaces are studied by means of Monte Carlo simulations. Coulomb-limited mobility and surface-roughness mobility are then isolated, applying Matthiessen’s rule. It is shown that the Coulomb-limited mobility due to the charges placed simultaneously at both interfaces is just the superposition of the effects produced separately at each interface by the charges. This effect can easily be modeled by adding the effects of each interface separately, using Matthiessen’s rule. Similar results are found in relation to surface-roughness mobility. In this case, the separate contributions of the two interfaces can also be added together to obtain a model where they are both taken into account.
Solid-State Electronics 01/2013; 79:92–97. DOI:10.1016/j.sse.2012.07.013 · 1.50 Impact Factor
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