Random-Dopant-Induced Drain Current Variation in Nano-MOSFETs: A Three-Dimensional Self-Consistent Monte Carlo Simulation Study Using “Ab Initio” Ionized Impurity Scattering
ABSTRACT A comprehensive simulation study of random-dopant-induced drain current variability is presented for a series of well-scaled n -channel MOSFETs representative of the 90-, 65-, 45-, 35-, and 22-nm technology nodes. Simulations are performed at low and high drain biases using both 3-D drift diffusion (DD) and 3-D Monte Carlo (MC). The ensemble MC simulator incorporates an ldquo ab initio rdquo treatment of ionized impurity scattering through the real-space trajectories of the carriers in the Coulomb potential of the random discrete impurities. When compared with DD simulations, the MC simulations reveal a significant increase in the drain current variability as a result of additional transport variations due to position-dependent Coulomb scattering that is not captured within the DD mobility model. Such transport variations are in addition to the electrostatic variation in carrier density that is alone captured within the DD approach. Through comparison of the DD and MC results, we estimate the relative importance of electrostatic and transport-induced variability at different drain bias conditions.
- SourceAvailable from: Yu Cao[show abstract] [hide abstract]
ABSTRACT: Random variations have been regarded as one of the major barriers on CMOS scaling. Compact models that physically capture these effects are crucial to bridge the process technology with design optimization. In this paper, 3-D atomistic simulations are performed to investigate fundamental variations in a scaled CMOS device, including random dopant fluctuation (RDF), line-edge roughness (LER), and oxide thickness fluctuation (OTF). By understanding the underlying physics and analyzing simulation results, compact models for random threshold (V th ) variations are developed. The models are scalable with device specifications, enabling quantitative analysis of circuit performance variability in future technology nodes. Using representative circuits, such as the inverter chain and SRAM cell, key insights are extracted on the trend of variability, as well as the implications on robust design. KeywordsThreshold variation-Random dopant fluctuation-Line-edge roughness-Oxide thickness fluctuation-Atomistic simulation-Predictive modeling-Inverter-SRAM performance variabilityJournal of Computational Electronics 04/2012; 9(3):108-113. · 1.01 Impact Factor
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ABSTRACT: Statistical variability is a major challenge for CMOS scaling and integration. In order to achieve variability aware design, it's critical important to reliably transfer device characteristics statistical variability information into compact models. A PCA based statistical compact modeling strategy is benchmarked against 'atomistic' device simulation and direct statistical parameter extraction strategy. The results indicate that PCA based approach may introduce considerable error in tail of distribution, which in turn may generate pessimistic or optimistic conclusions in statistical circuit simulation01/2009;
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ABSTRACT: Statistical variability (SV) presents increasing challenges to CMOS scaling and integration at nanometer scales. It is essential that SV information is accurately captured by compact models in order to facilitate reliable variability aware design. Using statistical compact model parameter extraction for the new industry standard compact model PSP, we investigate the accuracy of standard statistical parameter generation strategies in statistical circuit simulations. Results indicate that the typical use of uncorrelated normal distribution of the statistical compact model parameters may introduce considerable errors in the statistical circuit simulations.