Random-Dopant-Induced Drain Current Variation in Nano-MOSFETs: A Three-Dimensional Self-Consistent Monte Carlo Simulation Study Using “Ab Initio” Ionized Impurity Scattering

Dept. of Electron. & Electr. Eng., Glasgow Univ., Glasgow
IEEE Transactions on Electron Devices (Impact Factor: 2.36). 12/2008; 55(11):3251 - 3258. DOI: 10.1109/TED.2008.2004647
Source: IEEE Xplore

ABSTRACT A comprehensive simulation study of random-dopant-induced drain current variability is presented for a series of well-scaled n -channel MOSFETs representative of the 90-, 65-, 45-, 35-, and 22-nm technology nodes. Simulations are performed at low and high drain biases using both 3-D drift diffusion (DD) and 3-D Monte Carlo (MC). The ensemble MC simulator incorporates an ldquo ab initio rdquo treatment of ionized impurity scattering through the real-space trajectories of the carriers in the Coulomb potential of the random discrete impurities. When compared with DD simulations, the MC simulations reveal a significant increase in the drain current variability as a result of additional transport variations due to position-dependent Coulomb scattering that is not captured within the DD mobility model. Such transport variations are in addition to the electrostatic variation in carrier density that is alone captured within the DD approach. Through comparison of the DD and MC results, we estimate the relative importance of electrostatic and transport-induced variability at different drain bias conditions.

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    • "In the following, we adopt r c = 0.5 nm as a good compromise between the short-range scattering resolution and numerical efficiency [17]. "
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    ABSTRACT: This paper investigates the accuracy and issues of modeling carrier mobility in the channel of a nanoscaled MOSFET in the presence of discrete charges trapped at the channel/oxide interface. By comparing drift-diffusion (DD) and Monte Carlo (MC) simulation results, a quasi-local mobility model accounting for the complex scattering profile associated with a trapped carrier at the center of the channel is firstly derived. The accuracy of this model is evaluated on a test-bed 25-nm MOS transistor at low drain bias condition and for several applied gate biases. The issues in extending this mobility model to high drain biases regime and to the case of randomly positioned trapped charges are then discussed in the second part of this paper. Our findings show that DD simulations can maintain computational efficiency and accuracy at low drain biases, when a proper mobility model is used to describe the impact of discrete trapped charges. On the other hand, more complex corrections, that go beyond the simple mobility modification, are necessary to compensate the different carrier concentrations between DD and MC approaches at high drain biases.
    IEEE Transactions on Electron Devices 04/2014; DOI:10.1109/TED.2014.2312820 · 2.36 Impact Factor
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    • "High doping concentrations are required to keep short channel effects under control in nanometric bulk transistors, and therefore, carrier mobility is greatly reduced [2] [3] [4] [5] [6]. In addition, the random impurity effects in these devices are by no means negligible since they produce a considerable dispersion of fundamental parameters such as the threshold voltage and the sub-threshold slope [7]. In this context, new structures have been proposed to overcome these limitations. "
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    Solid-State Electronics 01/2013; 79:92–97. DOI:10.1016/j.sse.2012.07.013 · 1.51 Impact Factor
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    • "A high impurity density is necessary to keep SCEs under control and, as a consequence, carrier mobility is strongly reduced and the device performance degraded [1] [2] [3] [4]. In such short channel devices the random impurity effects in the active region of the transistor, which are known to be the most important source of statistical variability, are by no means negligible since they produce a spreading of fundamental parameters such as the threshold voltage and the subthreshold slope [5] [6] [7]. "
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    ABSTRACT: We have developed an advanced inversion charge model for both n-type and p-type symmetrical Double-Gate MOSFETs where quantum mechanical effects (QMEs) have been included. By doing so, the role of different crystallographic orientations was successfully taken into account. Self-consistent Poisson and Schrödinger simulators were used to check the accuracy of the model presented. As a starting point, a classical inversion charge centroid model was considered. Afterwards, an inversion charge model was developed including QMEs by means of a corrected oxide capacitance. The validity of the model was checked for the three common wafer orientations (1 0 0), (1 1 0) and (1 1 1) and for devices with different silicon layer (tSi) and oxide (tox) thicknesses. As it will be shown, the model reproduces correctly the simulation data both in the subthreshold and in the strong inversion operation regime.
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