Conference Paper

Code generation for the MPEG Reconfigurable Video Coding framework: From CAL actions to C functions

IETR Lab., Image & Remote Sensing Group, INSA de Rennes, Rennes
DOI: 10.1109/ICME.2008.4607618 Conference: Multimedia and Expo, 2008 IEEE International Conference on
Source: IEEE Xplore

ABSTRACT The MPEG reconfigurable video coding (RVC) framework is a new standard under development by MPEG that aims at providing a unified specification of current MPEG video coding technologies. In this framework, a decoder is built as a configuration of video coding modules taken from the standard ldquoMPEG toolbox libraryrdquo. The elements of the library are specified using the CAL actor language (CAL). CAL is a dataflow based language providing computation models that are concurrent and modular. This paper describes a synthesis tool that from a CAL specification automatically generates compilable C-code. Code generators are fundamental supports for the deployment and success of the MPEG RVC framework. This paper focuses on the automatic translation of CAL actions, which is the first step to a complete actor translation. The techniques described here enable to automatically generate C-code according to a finite set of rules. This approach has been used to obtain a C implementation of the IDCT module which is one element of the RVC library. The generated code is validated against the original CAL dataflow program simulated using the open dataflow environment.

  • [Show abstract] [Hide abstract]
    ABSTRACT: The standardization efforts of MPEG in video coding, originally had as main ­objective to guarantee interoperability of compression systems. This carried with it the possibility to reach another important objective, namely to wide and easy deployment of implementations of those standards. While at the beginning MPEG-1 and MPEG-2 were only specified by textual descriptions, with the increasing complexity of video coding tools, starting with the MPEG-4 set of standards, C or C++ specifications, called reference software, have also become a formal specification of the standards. However, descriptions composed of non-optimized non-modular software packages have shown limitations. Since in practice they are frequently the starting point of an implementation, system designers must rewrite these software packages not only to try to optimize performance, but also to transform such specifications into appropriate forms adapted to be the starting point of current system design flows.
    10/2011: pages 231-247;
  • [Show abstract] [Hide abstract]
    ABSTRACT: Modern embedded systems show a clear trend towards the use of Multiprocessor System-on-Chip (MPSoC) architectures in order to handle the performance and power consumption constraints. However, the design and validation of dedicated MPSoCs is an extremely hard and expensive task due to their complexity. Thus, the development of automated design processes is of highest importance to satisfy the time-to-market pressure of embedded systems. This paper proposes an automated co-design flow based on the high-level language-based approach of the Reconfigurable Video Coding framework. The designer provides the application description in the RVC-CAL dataflow language, after which the presented co-design flow automatically generates a network of heterogeneous processors that can be synthesized on FPGA chips. The synthesized processors are Very Long Instruction Word-style processors. Such a methodology permits the rapid design of a many-core signal processing system which can take advantage of all levels of parallelism. The toolchain functionality has been demonstrated by synthesizing an MPEG-4 Simple Profile video decoder to two different FPGA boards. The decoder is realized into 18 processors that decode QCIF resolution video at 45 frames per second on a 50 MHz FPGA clock frequency. The results show that the given application can take advantage of every level of parallelism.
    Signal Processing Image Communication 11/2013; 28(10). DOI:10.1016/j.image.2013.08.013 · 1.15 Impact Factor
  • Source
    [Show abstract] [Hide abstract]
    ABSTRACT: In 2004, a new standardization activity called reconfigurable video coding (RVC) was started by MPEG with the purpose of offering a framework which provides reconfiguration capabilities for standard video coding technology. The essential idea of RVC framework is a dynamic dataflow mechanism of constructing new video codecs by a collection of video coding tools from video tool libraries. With this objective, RVC framework is not restricted to specific coding standard, but defined at coding tools level with interoperability to achieve high flexibility and reusability. Three elements are normative in RVC framework: decoder description (DD), video tool library (VTL) and abstract decoder model (ADM). With these elements, a standard or new decoder is able to be reconfigured in RVC framework. This paper presents the procedure of describing a reconfigured decoder in DD, reusing and exchanging tools from VTLs and initializing ADM in the dataflow formalism of RVC framework. A decoder configuration which can be instantiated as AVS intra decoder configuration or other new decoder configurations in RVC framework is described as an example by using coding tools from China audio video coding standard (AVS) and MPEG series. It is shown that the process mechanism offered by RVC framework is versatile and flexible to achieve high reusability and exchangeability in decoder configurations.

Full-text (4 Sources)

Available from
May 29, 2014