Design centering scheme for robust SRAM cell design
ABSTRACT In this paper, a statistical approach for the optimal design of 6-T FinFET based SRAM cells considering the statistical distributions of gate length and silicon thickness of its transistors is presented. The corresponding statistical correlations of these two parameters are also considered. In this method, proper back-gate voltages for the SRAM transistors which maximize the yield against read, write, access and hold errors are determined. To assess the efficiency of the approach, the approach is applied to a 45 nm FINFET technology. The use of Monte-Carlo simulations shows the effectiveness of the method for increasing the yield of the FinFET SRAM cells. The proposed scheme is general and may be applied to other circuits.
- SourceAvailable from: Behzad Ebrahimi[Show abstract] [Hide abstract]
ABSTRACT: In this paper, an optimal approach for the design of 6-T FinFET-based SRAM cells is proposed. The approach considers the statistical distributions of gate length and silicon thickness and their corresponding statistical correlations due to process variations. In this method, a back-gate voltage is used as the optimization knob. With the help of particle swarm optimization (PSO), the back-gate voltages that maximize the yield of the SRAM array against read, write, and access time failures are found. It will be shown that, with this method, a very high yield is achieved.IEEE Transactions on Very Large Scale Integration (VLSI) Systems 11/2011; · 1.22 Impact Factor
Proceedings of the International Conference on Computer and Communication Engineering 2008 May 13-15, 2008 Kuala Lumpur, Malaysia
978-1-4244-1692-9/08/$25.00 ©2008 IEEE
Design Centering Scheme for Robust SRAM Cell Design
Masoud Rostami, Behzad Ebrahimi, Ali Afzali-Kusha
Nanoelectronics Center of Excellence, School of Electrical and Computer Engineering,
University of Tehran, Tehran, Iran
In this paper, a statistical approach for the optimal
design of 6-T FinFET based SRAM cells considering
the statistical distributions of gate length and silicon
thickness of its transistors is presented. The
corresponding statistical correlations of these two
parameters are also considered. In this method, proper
back-gate voltages for the SRAM transistors which
maximize the yield against read, write, access and hold
errors are determined. To assess the efficiency of the
approach, the approach is applied to a 45 nm FINFET
technology. The use of Monte-Carlo simulations shows
the effectiveness of the method for increasing the yield
of the FinFET SRAM cells. The proposed scheme is
general and may be applied to other circuits.
SRAM arrays are a major part of the chip area in
typical microprocessors. As memory will continue to
consume a large fraction of future designs, scaling of
memory continue to track the scaling trends of logic.
Unfortunately, decreasing the device dimensions will
lead to severe increase of parametric variation which
along with the trend of decreasing system supply and
transistor threshold voltages degrades the stability of
conventional six-transistor (6-T) SRAM cells .
Overcoming intra- and inter-die variations is emerging
as a challenge for VLSI designers and in recent years,
several schemes have been proposed to overcome
these challenges (see, e.g., , , .)
The FinFET  transistor structure has been
developed as an alternative to the bulk structure for its
improved scalability in submicron era . The gates on
either side of its fin can be tied together or they can be
electrically isolated to allow their independent
operation; this is achieved by selectively removing the
gate material in the region directly on top of the fin. In
the tied-gates operating mode, the two gates are biased
together to switch the FinFET on/off, whereas in the
independent-gates operating mode, they are biased
independently in a way that one gate is used to switch
the FinFET on/off and the other gate is used to adjust
the threshold voltage  and this offers dynamic or
static performance tunability which gives the designers
a great flexibility . These characteristics can be
utilized to improve the SRAM cell; as for example in
 authors proposed using this characteristic of
FinFET based SRAMs along with two wordlines. They
reported better cell stability with minimum area
Considering this, a statistical design centering
scheme for robust design of FinFET SRAM cells has
been proposed in this paper; the value of back-gate
voltages of the six transistors of the cell is found in a
way that the minimum read, write, access and hold
errors are observed. In optimization of these voltages,
the statistical distribution of gate length and silicon
thickness of the transistors of the cells was also
considered. The proposed scheme is general and may
be applied to other circuits.
This paper is organized as follows. In Section II, the
technology parameters and the size of transistors used
in the simulations are discussed. A review of the
stability criteria of the SRAM cells and its different
failure mechanisms are discussed in Section III. The
proposed design methodology for the SRAM cell is
described in Section IV where the experimental results
are also discussed. Finally, the conclusion is given in
Figure 1. Schematic of a conventional 6-T SRAM cell.
II. DEVICE PARAMETERS
Fig. 1 shows a typical 6-T FinFET based SRAM
cell. The nominal values of key design parameters are
summarized in Table I. For implementing the proposed
scheme, we used a 45nm FinFET technology . We
assumed that the pull-up and pass-transistors have one
fin and for decreasing the probability of read error, it
was decided to have pull-down transistors with two
fins. A triple-fin FinFET is shown in Fig. 2 .
Table 1 NOMINAL DEVICE PARAMETERS USED FOR HSPICE
L (Channel Length)
tox (Oxide Thickness)
tsi (Silicon Thickness)
VDD (Power Supply)
NBODY (Channel Doping)
Hfin (Fin Height)
VTH0 nmos typical (Threshold
Voltage of NFET)
VTH0 pmos typical (Threshold
Voltage of PFET)
Figure 2. Triple-fin FinFET structure .
Fig. 3 shows the SRAM array and its corresponding
parameters. A 128 column × 256 row memory array
which has a size of 32Kb has been assumed. The
wordlines and the bitlines are modeled as distributed
RC networks. The resistance and the capacitances of
wordline and bitline were derived from predictive
interconnect model for the 45nm technology node 
and is shown in Fig. 3. We did not include the sense
amplifiers in the simulations; but it is assumed that the
read operation is performed when a pre-specified
voltage difference (Δmin ≈ 0.1VDD) is produced
between the two bitlines.
III. FAILURE MECHANISM IN SRAM CELLS
A robust SRAM cell design requires a careful
balancing between different parameters in the presence
of many contradictory constraints. Here, we present a
brief review of the failure mechanisms in SRAM cells
and define some merits to assess them quantitatively.
Figure 3. SRAM circuit schematic and its parameters.
A. Read Failure
Figure 4. Unstable Read.
During the read operation of the cell shown in Fig.
1 (VL= 1 and VR=0), the voltage at node R (VR)
increases to a positive value VREAD, due to voltage
dividing between right access transistor (AR) and right
pull down transistor (NR). If VREAD is higher than
the trip point of the left inverter (VTRIP,RD), then the cell
flips while reading the cell and a read failure occurs
(Fig.4Error! Reference source not found.). If the
access and pull down transistors have the same
threshold voltage, the W/L (width/length) ratio of NR
to that of AXR will determine how high VR will rise.
The ratio is commonly referred to as the cell β ratio.
The read stability can be increased by upsizing the
pull-down transistor (increasing its fins) or decreasing
its threshold voltage by increasing its back-gate
voltage, which results in an area and leakage penalty
and/or decreasing the threshold voltage of the access
transistors which increases the delay. For a robust
SRAM cell design, the random variations in the
strengths of different transistors should also be taken
Figure 5. Read butterfly plot of a SRAM cell with back-gate
voltages of all transistors being zero is depicted. The Read SNM
is 38.5 mV.
Usually read SNM is used as a merit for the
stability of the cell against read failures. In
construction of butterfly curves of the cell in the read
operation, the AR and PR can be considered as parallel
transistors which degrades the gain of the inverters and
hence the butterfly curves became narrower. The
maximum length of a square which can be fit in to the
butterfly curves is a good merit for the static noise
margin of the memory . In Fig. 5, the read butterfly
curve of the cell are depicted while back-gate voltage
of all the transistors is zero. In this non-optimum point
of operation, the read SNM is 39 mV which is
relatively very low.
B. Access Time Failure
The cell access time (TACCESS) is defined as the time
required for producing a pre-specified voltage
difference (e.g. Δmin ≈ 0.1VDD) between the two
bitlines of the cell. If due to a parametric variation,
most importantly a threshold voltage variation, the
access time of the cell is longer than a maximum
tolerable limit (TMAX), an access time failure occurs.
The access failure is caused by the reduction in the
strength of the access and the pull-down transistors. In
other words access failure can be caused by an
increase in the threshold voltage of the AR and/or NR
transistors. Thus, the inter-die variation which changes
the parameters in the same direction may increase the
access failure, too . This is different from the read-
failure which only occurs in the case of intra-die
variation or in other words in the case that the strength
of neighboring transistors may change in different
Figure 6. Voltage values for a cell, with back-gate voltages of all
transistors being zero, are depicted while accessing the memory.
The voltage difference of bitlines in this case is 96 mV.
The amount of voltage difference between the two
bitlines of the cell, at the moment that wordline
deactivates, is a good merit for the stability of the cell
in regard to access failure. In Fig. 6, the voltage values
of bitlines and other related signals while reading the
cell is depicted. We assumed for this technology that
the wordline will be high for duration of 90 ps. In the
case that the backgate voltages of all the transistors are
zero, the voltage difference between the bitlines is
0.096 V, which may be acceptable.
C. Write Failure
When writing a "0" to a cell storing "1," the node
VL becomes discharged through BL to a lower value
(VWR) determined by the voltage division between the
left PMOS pull down transistor (PL) and the left
access transistor (AL). If the voltage of VL cannot be
reduced below the trip point of the right inverter (PR −
NR) (VTRIP,WR) within the time window that the
wordline is high (TWL), then a write failure occurs, Fig.
Figure 7. Unstable Write.
The variation in the device strengths due to random
variations in process parameters can increase the write
time. For example, if the threshold voltage of PL is
reduced and that of AXL is increased, the write time
will increase and a write failure may be observed .
Figure 8. Voltage values for a cell in the write operation. The x
axis is the value of the bitline voltage which is supposed to be
Usually, the maximum voltage value of the bitline
that is going to write '0' to a cell containing '1' is
considered a good merit for the stability of the cell in
regard to write error. In Fig.8, the voltage values of the
storage nodes in respect to the bitline's voltage, which
is supposed to be ideally zero, are depicted; the other
bitline is kept as VDD in this simulation. In the case that
the backgate voltages of pull-down, access, PL and PR
transistors are 0.4 V, 0.5 V, 0.5 V and 0.3 V
respectively, the write margin is around 0.64 V.
When there is a mismatch between right and left
sections of a cell, the write margin must be calculated
twice. One time for the case that VL=1, VR=0 and the
BLC is zero. In the second time, VL=0, VR=1 and BL
is zero. The write margin of the cell is the minimum of
these two values.
D. Hold Failure
In the stand-by mode, the VDD of the cell is lowered
to reduce the leakage power consumption .
However, if lowering VDD causes the data stored in the
cell to be flipped, then the cell is said to have failed in
the hold mode. As the supply voltage of the cell is
lowered, the voltage at the node storing "1" (suppose
node VL) also reduces. Meanwhile, for a low supply
voltage (when PL is not strongly "ON"), the leakage of
the pull-down NMOS (NL) reduces the voltage at node
VL, even below the supply voltage applied to the cell.
In this case, if the voltage at the node L is reduced
below the trip-point of the right inverter, then flipping
occurs and the data is lost in the hold mode (Fig. 9).
The supply voltage in the hold mode is chosen to
ensure the holding of the data under the nominal
conditions. However, the variations in the process
parameters can result in the device mismatch causing
hold failures. For example, if the threshold voltage of
NL reduces while that of PL increases (which
facilitates the reduction of the voltage at node L from
the applied supply voltage) and/or if the threshold
voltage of NR increases, while that of PR reduces
(increasing the trip-point of the right inverter), the
possibility of the data flipping in the hold mode
Figure 9. Unstable Hold.
The hold margin is usually taken as the static noise
margin of the cell while the cell is in the hold mode.
The butterfly curves of the cell operating in the hold
mode ( when the wordline is deactivated) is obtained
and the length's of the maximum square, that can be fit
in to it, is considered as the static noise margin of the
cell in the hold mode. The procedure is the same as
calculating the read noise margin, but this time, the
increase in the gain of the inverters makes the signal to
noise margin bigger. In the case that all the backgate
voltages of the FinFET transistors are kept at zero, the
hold margin is 0.1561 V (Fig. 10).
Figure 10. Hold Butterfly plot of a SRAM cell with back-gate
voltages of all transistors being zero is depicted. The Hold SNM
is 0.1561 V.
IV. METHODOLOGY AND RESULTS
Each transistor of the cell has few parameters that
can be changed during the design, for example its
back-gate voltage or number of its fins. Some of these
parameters are fixed when the technology is
determined; examples of such parameters are the
doping and the gate oxide thickness. All of these
parameters have statistical variations which should be
considered during a robust design of the cell. In
addition, a robust design against a range of variation
for a specific parameter, such as power supply noise,
may require a worst case design for that parameter.
Considering all these parameters for a robust design of
a cell with a brute force search needs a huge amount of
computation efforts which in some cases, it may be not
feasible. To overcome this challenge, we propose a
scheme which is explained next.
For reaching to the optimum yield against read,
write, access and hold errors; statistical design
centering was performed. There are lots of methods for
doing the job; depending on the application, the best
algorithm should be selected. A good review of these
methods can be found in . First, for giving a good
intuition to the reader, the Director’s simplicial
approximation method  is briefly explained in
section A. Then the probabilistic variables of SRAM's
cell is discussed in section B, and according to their
characteristics a proper statistical design centering
method is selected and applied in section C.
A. Director's Method
In this technique, starting from some points in the
acceptable area of parametric space, with linear search
at least n+1 nodes in the boundary of the desired space
is found, n is number of the parameters. The result of a
specific function is considered to be acceptable when it
is larger or equal to a specific value (e.g., in the write
operation of the SRAM, write margin must be bigger
than 0.4 V). The boundary of the desired space for a
function is defined as the collection of the points at
which the function has the result equal to the minimum
value of the condition while the other functions must
completely satisfy their constraints. (For example the
write function boundary is the collection of the point
that the write margin is exactly 0.4 and read, access
and hold criteria are all satisfied completely.) After
finding some points in the boundary of the space, a
convex hull with these points is constructed. The
largest polyhedron inscribed within it gives an
approximation of the desired space. Using a linear
search, more points on the boundary is found and the
convex hull is updated. The process thus provides a
monotonic lower bound on the yield. The center and
the radius of the hypersphere can be used to determine
the centered optimal point and its tolerance,
B. SRAM's Probabilistic Variables
As shown in , there exists a statistical
dependency between the gate lengths of adjacent
devices. The channel length and the silicon thickness
of submicron FinFETs have also been considered as
the major sources of the parametric variations .
Usually, the variance for these two parameters is
considered to be one tenth of the designed value .
These two kinds of variations, which stem from
imperfections in the lithography process, usually have
a Gaussian distribution and their values show a
statistical dependency between each others .
Note that the closer the transistors are, the greater their
statistical dependence is. In , the channel width
covariance of neighboring transistors was considered
to be 1. In other words, it is almost impossible to have
a transistor with large channel length in the
neighborhood of a transistor with small channel length.
If it is assumed that the transistors of SRAM cell have
a perfect statistical dependence, a major source of
intra-die variation will be solved. In other words, there
will be no mismatch between the six transistors and the
cell will be almost always stable, which is a trivial
solution. In this paper, the covariance of L and Tsi of
FinFET transistors in a cell has been assumed to be 0.5
and the statistical dependence between adjacent cells
was assumed negligible.
In any SRAM cell, we have three different
transistors that their relative strength should be
optimized. In this work, we used the double gate
FinFETs where the back-gate voltages of these three
transistors are used in our design centering technique.
To consider the imperfection in the circuit that
produces these three voltages, we also considered a
variance of 0.05V for each of them. A summery of
statistical variables of this design can be found in
Table 2 which implies a design space with 18
TABLE 2. MEAN, VARIANCE, AND COVARIANCE OF THE
STATISTICAL VARIABLES USED IN THE DESIGN.
C. Seifi's Method
The Director’s simplicial approximation method has
some shortcomings. First, it was indirectly assumed
that all of the variables have independent statistical
behaviors. Second, this technique also requires the
convexity of the acceptable region which may not be
always the case, thus other feasible methods should be
used. Recently, many research efforts have been
devoted to the optimal design of integrated circuits
considering the statistical variation. (e.g. , )
These techniques do not assume independent statistical
behaviors. The technique proposed in  considers
the parameters as dependant Gaussian variables. Since
in this work, we make the same assumptions for our
parameters, we used its proposed technique.
In this algorithm, given the covariance matrix of the
input parameters (can be constructed by Table 2), the
statistical distance of any nominal point in the
parametric space from the surface of the desired space
(tolerance) can be found. For doing that, at first using
the iterative Eq. 1, the point in the boundary of
equation (x*) that has the minimum distance to the
nominal point (μ) is found by the following iterative
C is the covariance matrix of the input parameters,
G is the value of the first derivative of the condition
and g(.) is the condition equation, itself. Finally βk
should be found by the below equation.
The above equation converges quickly and yields x*
and β which the later is the minimum statistical
distance of nominal point from the boundary of the
condition. For example, if the distance (β) of the
nominal point from the surface of the condition is 1, 2
and 3, the yield of the system in respect to that
condition will be 52.4%, 93.2% and 99.6%,
As it can be seen from the above equations, the
value of the first derivative of the condition in some
points is required, which can be easily calculated by
numerical solutions from the value of the main
Repeating the above procedure for all the
conditions, the minimum distance of any point from
the boundaries of all the conditions is found; which we
called them βread, βwrite, βaccess and βhold. For reaching to
the maximum yield, a cost function is defined (Eq. 3).
αread, αhold, αwrite and αaccess are the relative weight of
read, hold, write and access errors. In this paper, it was
assumed that the all of them have the same importance,
so the weight coefficients were taken equal.
For implementing the proposed method, a code in
MATLAB changes the parameters of circuit model in
CG CG g x
several HSPICE netlists as is required by the design
centering algorithm. Then the HSPICE simulator is
called and the transient analysis is performed to check
whether read, write, or hold error have been occurred
and if they are not occurred their corresponding noise
margin is calculated. For doing this task, the result of
transient analysis are first loaded to MATLAB with the
help of HSPICE toolbox, and then read, write, access
and write margins are calculated automatically. These
margins are the results of complex functions that
should be optimized, by changing the backgate
Thus, the problem converts to finding the maximum
of the cost function in the design space. Any linear or
genetic search can be applied for solving this kind of
max-min problems. The genetic algorithm, however, is
usually faster . So, for optimization, the value of
the cost function is then taken as the fitness function of
the genetic algorithm. Every combination of the six
back-gate voltages is considered as a member of the
population. After around six generations, the algorithm
converges to the solution with the maximum yield.
Note that in the 6-T structure, we have only three
different transistors. This, however, does not mean that
the design centering can be performed in a nine-
dimensional space. The reason is that the values of the
similar transistors may change in different direction in
the manufacturing process. This symmetry however
leads to only three different final centered (optimal)
values. In other words, the desired space is
symmetrical to three different superplanes. Finally, it
should be noted that there exist other sources of
parametric variation besides the channel length and the
silicon thickness. For the state of the art technology,
they however may be neglected . One of these
sources is random dopant fluctuations in the channel.
The effect of this fluctuation is minimized due to the
fact that the channel in the double gate devices is
undoped or mostly-undoped . In the cases that this
effect should be considered, it should be remembered
that, in the state of the art technologies, this effect
causes the threshold voltage not to have a Gaussian
distribution  it is shown that the distribution of
threshold voltage mostly resembles the discrete
Poisson distribution . For these cases, other
proposed methods such as  should be used.
In Table 3, the results of the proposed technique for
the optimal values of the back gate voltages of the
transistors can be found, with this optimal value the
yield of the cell will be around 82%. The results were
also double-checked by a rigorous Monte-Carlo
simulation with more than 5 times of computation
TABLE 3. BACK GATE VOLTAGES OF THE OPTIMAL CELL (NOTE
THAT PD TRANSISTORS HAVE 2 FINS)
Back Gate Voltage
A method for optimizing the design of double-gate
FinFET based SRAMs was presented. The method
used a two-stage optimization process to maximize the
yield. It was shown that by modulating the back-gate
voltage of the three kinds of transistors in the SRAM
cell, one can reach a very high yield against read,
write, access and hold errors. The final results have
also been verified by Monte-Carlo simulation.
 T.Cakici et al, "FinFET Based SRAM Design for Low Standby
Power Applications," ISQED, 2007, pp. 127-132.
 H. Ananthan, A. Bansal and K. Roy. "FinFET SRAM - device
and circuit design considerations," ISQED, 2004, pp. 511 –
 H. Chang and S. S. Sapatnekar, "Statistical Timing Analysis
Under Spatial Correlations," IEEE Transactions on Computer-
Aided Design of Integrated Circuits and Systems, vol. 24, no. 9,
pp. 1467 – 1482, September 2005.
 A. Bansal, et al , "Device-Optimization Technique for Robust
and Low-Power FinFET SRAM Design in NanoScale Era,"
IEEE Trans. on Electron Dev. June 2007.
 S.H. Tang et al, "FinFET-a quasi-planar double-gate
MOSFET," ISSCC Digest of Technical Papers, pp. 118-1 19,
 L. Chang, "Extremely Scaled Nano-CMOS Devices",
Proceedings of the IEEE, November 2003.
 Z. Guo, S. Balasubramanian, R. Zlatanovici, T. J. King and B.
Nikolić, "FinFET-Based SRAM Design," ISLPED’05, August
pp. 8–10, August2005.
 A. Datta, "Modelling and Circuit Synthesis for Independently
Controlled Double Gate FinFET Devices," IEEE Trans. On
Computer Aided Design of Integrated Circuits and Systems,
 O. Thomas, M. Reyboz, M. Belleville, " Sub-1V, Robust and
Compact 6T SRAM cell in Double Gate MOS technology,"
IEEE International Symposium on Circuits and Systems, pp.
2778-2781, May 2007.
 Predictive Technology Model (PTM) [Online]. Available:
 E. Seevinck, R. List, and J. Lohstroh, "Staic-Noise Margin
Analsys of MOS SRAM Cells," IEEE JSSC, vol. SC-22,
pp.748-754, Oct. 1987.
 S. Mukhopadhyay et al., "Modeling of failure probability and
statistical design of SRAM array for yield enhancement in
nanoscaled CMOS," IEEE Trans. Comput.-Aided Des., vol. 24,
no. 12, pp. 1859–1880, Dec. 2005.
 S. Mukhopadhyay, K. Kim, H. Mahmoodi and K. Roy, "Design
of a Process Variation Tolerant Self-Repairing SRAM for
Yield Enhancement in Nanoscaled CMOS," IEEE Journal of
Solid State Circuits, vol. 42, no. 6, JUNE 2007.
 J. W. Bandler, et al., "Circuit Optimization: the State of the
Art," IEEE Transaction on Microwave Theory and Techniques,
Vol 36, no. 2, February 1988.
 S. Director and G. Hatchel, "The simplicial approximation
approach to design centering," IEEE Transaction on Circuits
and Systems, July 1977.
 R. Brayton, S. Director and G. Hatchel, "Yield Maximization
and worst-case design with Arbitrary Statistical Distributions,"
IEEE Transaction on Circuits and Systems, September 1980.
 A. B. Kahng, S. Muddu and P. Sharma, "Detailed placement for
leakage reduction using systematic through-pitch variation,"
International Symposium on Low Power Electronics and
 A. Seifi, K. Ponnambalam and J. Vlach, "Probabilistic Design
of Integrated Circuits with Correlated Input Parameters," IEEE
Transaction on Computer Aided Design of Integrated Circuits
and Systems, vol.18, no. 8, August 1999.
 J. Singh, et al "A Scalable Statistical Static Timing Analyzer
Parameter Variation", IEEE Tran. On Computer Aided Design
of Integrated Circuits and Systems, vol. 27, no. 1, January
 Y. T. A. Khalifa, "Design centering of analog circuit's
component values using parallel genetic algorithms", ICECS,
 M. Chiang, et al , "Random Dopant Fluctuation in Limited-
Width FinFET Technologies", IEEE Trans. On Electron
Devices, August 2007.
 S. Toriyama, et al , "Probability Distribution functions of
threshold voltage fluctuations due to random impurities in
deca-nano MOSFETs," Physica E, Vol .19, no. 1/2, pp. 44-47,
 K. Ponnambalam, "Yield optimization with correlated design
parameters and non-symmetrical marginal distributions",
Non-Gaussian and Gaussian