Conference Paper

Design centering scheme for robust SRAM cell design

Nanoelectron. Center of Excellence, Univ. of Tehran, Tehran
DOI: 10.1109/ICCCE.2008.4580730 Conference: Computer and Communication Engineering, 2008. ICCCE 2008. International Conference on
Source: IEEE Xplore

ABSTRACT In this paper, a statistical approach for the optimal design of 6-T FinFET based SRAM cells considering the statistical distributions of gate length and silicon thickness of its transistors is presented. The corresponding statistical correlations of these two parameters are also considered. In this method, proper back-gate voltages for the SRAM transistors which maximize the yield against read, write, access and hold errors are determined. To assess the efficiency of the approach, the approach is applied to a 45 nm FINFET technology. The use of Monte-Carlo simulations shows the effectiveness of the method for increasing the yield of the FinFET SRAM cells. The proposed scheme is general and may be applied to other circuits.

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    ABSTRACT: In this paper, an optimal approach for the design of 6-T FinFET-based SRAM cells is proposed. The approach considers the statistical distributions of gate length and silicon thickness and their corresponding statistical correlations due to process variations. In this method, a back-gate voltage is used as the optimization knob. With the help of particle swarm optimization (PSO), the back-gate voltages that maximize the yield of the SRAM array against read, write, and access time failures are found. It will be shown that, with this method, a very high yield is achieved.
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems 11/2011; · 1.22 Impact Factor

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May 31, 2014