Conference Paper

A system-level perspective for efficient NoC design

Dept. of Electr. Eng., Princeton Univ., Princeton, NJ
DOI: 10.1109/IPDPS.2008.4536409 Conference: Parallel and Distributed Processing, 2008. IPDPS 2008. IEEE International Symposium on
Source: IEEE Xplore

ABSTRACT With the advent of chip multiprocessors (CMPs) in mainstream systems, the on-chip network that connects different processing cores becomes a critical part of the design. There has been significant work in the recent past on designing these networks for efficiency and scalability. However, most network design evaluations use a stand-alone network simulator which fails to capture the system-level implications of the design. New design innovations, which might yield promising results when evaluated using such stand-alone models, may not look that attractive when evaluated in a full-system simulation framework. In this work, we present GARNET, a detailed network model incorporated inside a full-system simulator which enables system-level performance and power modeling of network-level techniques. GARNET also facilitates accurate evaluation of techniques that simultaneously leverage the memory hierarchy as well as the interconnection network. We also discuss express virtual channels, a novel flow control technique which improves network energy/delay by creating virtual lanes in the network along which packets can bypass intermediate routers.

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