Conference Paper

Efficient construction and implementation of short LDPC codes for wireless sensor networks

Dept. of Microelectron. Eng., Univ. Coll. Cork, Cork
DOI: 10.1109/ECCTD.2007.4529693 Conference: Circuit Theory and Design, 2007. ECCTD 2007. 18th European Conference on
Source: IEEE Xplore

ABSTRACT Wireless sensor networks gained a lot of attention in recent years due to their widespread applications. Reliability of data communication and power saving are paramount for applications which use wireless sensor network technology. We propose two classes of short quasi-cyclic LDPC codes suitable for implementation on a resource constrained system. The codes we propose are easy to encode and their decoding performance compares well with random LDPC codes with the same parameters. We implement our codes on a 25 mm mote platform provided by Tyndall and compare them with Viterbi coding schemes.

0 Bookmarks
 · 
27 Views
  • Source
    [Show abstract] [Hide abstract]
    ABSTRACT: One of the key factors underlying the popularity of low-density parity-check (LDPC) codes is its iterative decoding algorithm which is amenable to efficient analog and digital implementation. However, different applications of LDPC codes (e.g. wireless sensor networks) impose different sets of constraints which include speed, bit error rates (BER) and energy efficiency. Our previous work reported an algorithmic framework for designing margin propagation (MP) based LDPC decoders where the BER performance can be traded off with its energy efficiency. In this paper we present an analog current-mode implementation of an MP-based (32;8) LDPC decoder. The implementation uses only addition, subtraction and threshold operations and hence is independent of transistor biasing and robust to variations in environmental conditions (e.g. temperature). Measured results from prototypes fabricated in a 0.5m CMOS process verify the functionality of a (32;8) LDPC decoder and demonstrate superior BER performance compared to the state-of-the-art analog min- sum decoder at SNR greater than 3.5 dB. Index Terms—error-correction circuits, low-density parity- check (LDPC) decoder, margin propagation (MP), analog de- coders, current-mode circuits
    International Symposium on Circuits and Systems (ISCAS 2011), May 15-19 2011, Rio de Janeiro, Brazil; 01/2011