Conference Paper

Measurement of Nano-Displacement Based on In-Plane Suspended-Gate MOSFET Detection Compatible with a Front-End CMOS Process

CEA-LETI, Grenoble
DOI: 10.1109/ISSCC.2008.4523192 Conference: Solid-State Circuits Conference, 2008. ISSCC 2008. Digest of Technical Papers. IEEE International
Source: IEEE Xplore

ABSTRACT The first front-end CMOS co-integration based on the lateral SGMOSFET presented in this paper demonstrates the benefit of a co-integration approach for NEMS devices. Performance using this device is compared to that obtained with a standalone ASIC. The next step will consist of replacing equivalently the input transistor of the ASIC cascode structure by the SGMOSFET.

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    • "YBRID nanoelectromechanical system (NEMS) devices such as the suspended-gate field-effect transistor (FET) (SGFET) have attracted attention in the area of logic circuits because of their merit of low power consumption [1]–[3]. Moreover, such NEMS-based devices have also been applied in nonvolatile memory devices, sensors to detect nanometerscale displacement, and resonator applications [4], [5]. For another practical and multifaceted application, the convergence technology of NEMS and CMOS has become important as it is hoped to utilize the distinctive advantage created by that convergence. "
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    ABSTRACT: Bendable-channel fin field-effect transistor (FET) (FinFET) (BC-FinFET) is presented for the basic logic family that includes nand, nor , and pass gate. The BC-FinFET can replace the suspended-gate FET (SGFET), and its function is very similar to that of a double-gate MOSFET. The BC-FinFET is composed of an n-type and p-type MOSFETs, and hence, it can be applicable for logic circuits. Numerical simulations based on elementary characteristics extracted from the fabricated BC-FinFET have been carried out for nand and nor circuits from an input-output characteristics' point of view. The proposed architecture can improve the standby and dynamic power consumption by reduction of the number of SGFETs and the size of the chip, while improving circuit performance.
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    ABSTRACT: This paper proposes, the investigation of the Suspended Gate Field-Effect Transistor (SG-FET) small-slope switch based on a hybrid numerical simulation approach combining ANSYSTM Multiphysics and ISE-DESSISTM in a self-consistent system. The proposed numerical simulations uniquely enable the investigation of the behavior and the physics of complex micro-electro-mechanical/solid-state devices, such as the SG-FET. Abrupt switching as well as the effect of trapped charges in the gate dielectric are demonstrated. The numerical data serve to calibrate an analytical EKV-based SG-FET model, which is then used to design and originally simulate a sub-micron (90 nm) scaled SG-FET complementary inverter. It is shown that, due to abrupt switching in the subthreshold region and electro-mechanical hysteresis, the SG-FET inverter could deliver a significant power saving (1–2 decades reduction of inverter peak current and practically no leakage power) compared to traditional CMOS inverter.
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