A low power CMOS CORDIC processor design for wireless telecommunication

Abstract

A CORDIC processor for wire telecommunication is integrated in a 0.5 mum CMOS technology. The CORDIC (coordinate rotation digital computer) processor reduces the circuit complexity by performing a sequence of elementary rotations using shift and add operations without multiplications. Hard wired-logic eliminates the shifter and includes pre-calculated arctan angle values. The average power consumption is 76 mW with 50 MHz clock and 5 V power supply. The fabricated modulator consumes 24 mW at 61.44 MHz sampling rate and 5 V power supply.

Full text

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A Low Power CMOS CORDIC Processor Design
for Wireless Telecommunication

Young Bok Kim,Yong-Bin Kim
Dept. of Electrical and Computer Engineering
Northeastern University
Boston, MA, USA
{youngbok, ybk}@ece.neu.edu
James T. Doyle
Principal Design Engineer
National Semiconductor .Coporation
Longmont, CO, USA
Jim.doyle@nsc.com


This paper presents a power-efficient CMOS CORDIC
processor design using 0.5µm CMOS process.
Abstract—A CORDIC processor for wire telecommunication is
integrated in a 0.5µm CMOS technology. The CORDIC
(coordinate rotation digital computer) processor reduces the
circuit complexity by performing a sequence of elementary
rotations using shift and
multiplications. Hard wired-logic eliminates the shifter and
includes pre-calculated arctan angle values. The average power
consumption is 76mW with 50MHz clock and 5V power
supply. The fabricated modulator consumes 24mW at
61.44MHz sampling rate and 5V power supply
add operations without
I.
INTRODUCTION
The advent of third generation standards (3G) has
created new demands on multimode systems that support
various modulation formats such as CDMA and WCDMA
[1]. To achieve multi mode operation, transmitters must
accommodate constant envelop signals as well as non-
constant envelop signals [2]. To avoid distorting non-
constant envelops, conventional transmitters must employ
linear (class-A) or use predistortion techniques to linearize
slightly saturated (class-AB)
implementations sacrifice power efficiency and result in
decreased battery life. Furthermore, I/Q based transmitter
design may be problematic in multi-band operation since
baseband mixing produces unwanted spurious signals.
amplifiers. Both
Fortunately, a polar modulation offers an alternative for
multimode and multiband operations [3]. Figure 1 depicts a
high level architecture abstraction of a polar transmitter for
WCDMA. The shaded block shows a polar modulator
which consists of a CORDIC processor, interpolators, a
barrel-shifter, and a DAC-PWM generator. The digitized
amplitude envelope and the synchronized phase-modulated
RF carrier are recombined at the power amplifier to produce
linear and efficient RF transmission.
In burst-mode communication systems, a rapid carrier is
crucial. Therefore, a fast rectangular-to-polar conversion of
the CORDIC processor is desired. Delay-matching of
amplitude and phase is crucial since the restoration of the
transmitted data at the PA (Power Amplifier) may be
imperfect if the delays are unmatched.


RF-PA
Vbat
I
Q
Modulator
I/Q
CORDIC
A
R
Barrel S.
Synthesizer
PWM
TX_in
TX_out
VCO
DACInterpolator
Interpolator

Figure 1. Polar transmitter architecture for WCDMA.

II.
CORDIC ARCHITECTURE
There are two well-known implementations for a
rectangular to polar coordinate conversion. One method
uses a ROM lookup table with both real and imaginary
components as inputs. This is practical for lower accuracy
requirements as the ROM size grows exponentially with an
increasing number of input bits. The other approach is the
CORDIC processor [4] which realizes low-cost systems by
reducing system complexity. The CORDIC arithmetic
technique makes it possible to perform two dimensional
rotations using simple hardware components without
multipliers.
A distinct feature of the CORDIC algorithm is its use of
a sequence of elementary rotations to realize a variety of
complicated and non-linear functions. Each rotation requires
a simple simultaneous shift and adds operations. By
unfolding the iterations for an elementary rotation, a
pipelined CORDIC array processor is realized.
A. CORDIC Vectoring Mode for Polar Modulation
The CORDIC algorithm performs a planar rotation
which transforms a vector (Xi, Yi) into a new vector (Xj,
Yj) as shown in Fig. 2a.

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X
j
j
Target vector
X
Y
i
i
Y
X
θ
Initial vector
Y
X
Y
i
i
Y
X
Initial vector
Target vector
θ

(a) (b)
Figure 2. Vectoring mode for polar modulation.

Using a matrix form, a planar rotation for a vector of
(Xi, Yi) is defined as








−
=






i
i
j
j
Y
X
Y
X
θθ
θθ
cos sin
sincos
(1)
The θ angle rotation is executed in several steps. Each
step is defined in Table I and modified by eliminating the
cosθn factor as








−
=




+
+
n
n
n
n
n
n
n
Y
X
Y
X
1 tan
tan1
cos
1
1
θ
θ
θ
(2)
Implementation of (2) requires three multiplications.
Two multipliers are eliminated by selecting the angle steps
such that the tangent of a step is a power of 2. The angle for
each step is given by




=
n
n
2
1
arctan
θ
(3)
All summed iteration-angles are equal to the rotation
angle θ.
θ θ =
n
∑
=0n
∞
n S
,



≥+
<−
=
01
01
n
n
n
Y if
Y if
S
(4)
Define a variable Z which represents the part of the
angle θ as given in (5).
∑
=
i
+
−=
n
in
Z
0
1
θθ
(5)
These results in
n
nn
S
−
=
2 tanθ
(6)
Combining (2) and (6) gives










−
=




−
−
+
+
n
n
n
n
n
n
1
n
n
n
Y
X
S
S
Y
X
2
21
cos
1
1
θ
(7)
The cosθn coefficient is eliminated by pre-computing the
final result (assume that n = 8).
607259. 0
2
1
arctancos
0
≈












=∏
n
∞
=
n
K
(8)

TABLE I.
10-BITS BINARY VALUES FOR ARCTAN (2-I)
Step
1
arctan
arctan(20)
Angle (degree)
45.0000
10-bits binary
7F = 00 0111
1111
2 arctan(2-1) 26.5651 4B = 00 0100
1011
3 arctan(2-2) 14.0362 27 = 00 0010
0111
4 arctan(2-3) 7.1250 14 = 00 0001
0100
5 arctan(2-4) 3.5763 A = 00 0000
1010
6 arctan(2-5) 1.7899 5 = 00 0000
0101
7 arctan(2-6) 0.8952 2 = 00 0000
0010
8 arctan(2-7) 0.4476 1 = 00 0000
0001

Ignoring the congregate constant K, CORDIC performs
the following formulae.
n
n
nnn
YSXX
2
1
2−
+
−=

n
n
nnn
XSYY
2
1
2−
+
+=
(9)
)2arctan(
1
n
nnn
SZZ
−
+
−=

As shown in Fig. 2b, the CORDIC computes
[]












+=
i
i
iijjj
X
Y
YX
K
ZYXarctan, 0,
1
,,
22
(10)
where the arctan is pre-calculated.
B. Polar Pre-/Post-processing for WCDMA Transmitters
Since I/Q data-streams’ polarity is always positive due
to the DAC’s input, the origin is moved to the center of data
angle as shown in Fig. 3a. Then performing a quadrant
move shifts everything to the first quadrant as in Fig. 3b. In
post processing, the CORDIC processor recovers the
original quadrant and scales the congregate constant.
C. Rectangular to Polar CORDIC Architecture
A CORDIC element (CE) architecture is shown in Fig.
4. The datapath of the CE has 2-bits fixed point extension
which reduces truncation errors. Using cyclic convolution
provides the advantages of high computing parallelism and
low computation complexity. A parallel structure shown in
Fig. 5 consists of an array of CEs, each of which performs a
computation in parallel and is separated by registers to form
a pipelined structure.
The CE is the kernel of the CORDIC processor and its
primary function is to perform (9). The rectangular to polar
CORDIC accepts three input variables Xi, Yi, and Zi and
generates the output Xj, Yj, and Zj. It is operated in the
vectoring mode where variable Yi is forced to zero.

Page 3

X’
Y’
Q2Q1
Q3Q4
X’
X
Y’Y

(a) (b)
Figure 3. Pre-processing for a polar transmitter

From the hardware implementation point of view, this
operation is carried out using only shift and add operations
since multiplication of any quantity by 2-i is a shift of the
binary representation of the quantity by i-bit to the right.

-i
i i
-s x 2
-i
i i
s y 2
iy
y
i
-1 if < 0
+1 if >= 0
=
i+1 i+1i+1
zyx
Register i+1
CE i
i i
s a
is
iz
iy
ix

Figure 4. CORDIC element architecture abstraction.

As a result, all the evaluation procedures in CORDIC are
computed as a vector rotation in three coordinate systems
with an iterative unified formulation. The main components
of each CE are three adders, a shifter, a look-up table, and a
register. Since the function of the shifter in the pipeline is
fixed, the shift operation is implemented by wiring.
Moreover, the lookup table is replaced with hardwired logic
because each stage has a congregate constant rather than a
lookup table. Therefore, only three adders and a register are
required for a CE. Figure 5 depicts the entire design, and the
pseudo-rotation and the scaling factor blocks are very fast
parallel, pipeline structures. Since the RF digital baseband
output is unsigned binary and is the input of the CORDIC
processor, the unsigned values are converted to signed
binary by moving the origin. The pre-processing module
also performs a shift to quadrant one from the other
quadrants. The function of the post-processing block is to
scale the magnitude and to recover the original quadrant. To
do this the post-processing stage consists of adders and
wired-shifters.
D. Post-processing for WCDMA requirements
For larger word sizes, it is not economical to extend the
sampling rate from 8 to 32 times per cycle for WCDMA
input data using the direct ROM approach. Therefore, an
unsigned linear interpolation technique is used where the
distance between tabulated points is uniform.
Arctan 1/8
Arctan 1/16
Arctan 1/32
Arctan 1/4
Arctan 1/2
Arctan 1
CE 3
CE 4
CE 5
CE 6
CE 7
CE 8
CE 2
Pipelining
8-latency
Scaling Magnitude
Quadrant recovery
Wired logic
Origin move
Quadrant-1 move
0-latency
Pre-processing
Post_processing
2-latency
10-latency
jjj
ZXY
Arctan 1/128
Arctan 1/64
iii
ZYX
CE 1
Wired-shift + Adder

Figure 5. CORDIC processor architecture abstraction.

The interpolation method reduces the clock frequency for
CORDIC and the interpolators except for the counter, which
in turn decreases the power dissipation of these blocks by
factor of 4. The output of the barrel-shifter block reflects a
gain from the external inputs. There is an overflow signal
which indicates the output of the DAC-PWM module is out-
of-range, and the output is fixed as the maximum value. To
match the delays of the amplitude and angle, registers are
used at the final stage. The angle ports have additional
MUXes for serial- and parallel-outputs. The delay difference
is less than 1ns. The DAC-PWM module in Fig. 1 converts
parallel data to serial data. This makes the switch mode
regulator simpler.
III. SIMULATIONS AND EXPERIMENTAL
RESULTS
To simulate and verify the CORDIC in the modulator,
the input data is generated by a digital I/Q modulator
implemented using an Altera Flex10K FPGA. The 10-bit
CORDIC processor and other post-processing blocks are
modeled in Verilog HDL and are fully synthesized. The
datapath of CORDIC core consists of 0-latency pre-
processing, 8-latency pipeline, and 2-latency post-
processing. To integrate all components of the polar
transmitter, the design is mapped onto a 0.5µm four-metal
CMOS technology. The layout uses the standard cell based
design flow of Apollo with 80% core utilization
(1.1x1.3mm2, 10,000 gates). The nominal supply voltage for
core cells is 5V. The average power consumption of the
proposed architecture without low power circuit techniques
is about 24mW with a 61.44MHz clock frequency. Table II
shows the vectoring mode average power dissipation
comparison with [5]. Figure 6 shows the die photo of the
CORDIC for a digital polar modulator. Table II lists the

Page 4

errors between the results and the calculations caused by
truncation and limited pipeline stage. X, Y and X’, Y’ are
the unsigned and the signed 10-bits inputs, respectively (See
Fig. 3a). R is the polar magnitude from the origin (512,
512), and A is the polar phase angle whose maximum value
1024(0 indicates 360°). The error between the calculation
and the results for the modulator including channel noise is
tolerable during demodulating. Note that the % error of A(c)
is deviation from 90o.

IV. CONCLUSION
Due to CORDIC’s regularity and simplicity, the
proposed transmitter architecture is very suitable for VLSI
implementation. The CORDIC architecture proposed in this
paper adopts a hard-wired pipeline strategy to increase the
performance and reduce the size at the architectural level.
The separate distribution of angle constants to each adder
also permits a hardwire solution instead of using a lookup
table, and all the shifters are hard-wired. Moreover, the
interpolation method reduces the sampling rate of the
CORDIC and the interpolators except for the counter, and,
in turn, decreases the power dissipation of those blocks by
factor of 4. The delays-matching of amplitude and phase is
accomplished in 1ns. The proposed digital polar modulator
is designed, integrated, and fabricated using 0.5µm CMOS
process; it is tested, and used successfully for CDMA
applications. The modulator is a good reference for a low
power communication VLSI chip integration, especially
SoC (Systems-on-Chip).





Figure 6. The CORDIC die photo for digital polar modulator





TABLE II.
POST-LAYOUT SIMULATION RESULTS AND CALCULATIONS
Input
X (X’)
612 (100)
Output
R(o)
112
Calculation
R(c)
111.80
Error (%)
R(c)
0.18
Y (Y’)
562
(50)
612 (100)
A(o)
75
A(c)
85.33
A(c)
4.04
612 (100) 142 127 141.42 128.0
0
170.6
7
256.0
0
341.3
3
384.0
0
426.6
7
0.41 0.39
612 (100) 712 (200) 224 181 223.61 0.17 4.04
512
(0)
412
(-100)
412
(-100)
412
(-100)
712 (200) 200 255 200.00 0 0.39
712 (200) 224 331 223.61 0.17 4.04
612 (100) 142 385 141.42 0.41 0.39
562
(50)
112 437 111.80 0.18 4.04

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