Process-Variation Statistical Modeling for VLSI Timing Analysis
Nat. Taiwan Univ., TaipeiDOI: 10.1109/ISQED.2008.4479828 Conference: Quality Electronic Design, 2008. ISQED 2008. 9th International Symposium on
Source: IEEE Xplore
SSTA requires accurate statistical distribution models of non-Gaussian random variables of process parameters and timing variables. Traditional quadratic Gaussian model has been shown to have some serious limitations. In particular, it limits the range of skewness that can be modeled and it can not model the kurtosis. In this paper, we presented complex-coefficient quadratic Gaussian polynomial model and higher order Gaussian polynomial model to resolve these difficulties. Experimental results show how our methods and new algorithms expose some enhancements in both accuracy and versatility.
Conference Paper: Residue Arithmetic for Variation-Tolerant Design of Multiply-Add Units[Show abstract] [Hide abstract]
ABSTRACT: This paper investigates the residue arithmetic as a solution for the design of variation-tolerant circuits. Motivated by the modular organization of residue processors, we comparatively study the sensitivity of residue arithmetic-based and binary processors to delay variations, and in particular the impact of delay variations onto the maximum critical path. Experiments are performed on two multiply-add (MAC) circuits based on residue and binary arithmetic. Results reveal that residue arithmetic-based circuits are up to 94% less sensitive to delay variation than binary circuits, thus leading to increased timing yield.PATMOS; 01/2009
Conference Paper: Variation-tolerant Design Using Residue Number System.[Show abstract] [Hide abstract]
ABSTRACT: In this paper the use of residue arithmetic is proposed as a technique to reduce delay variation in adders. It is found that the use of residue arithmetic offers significant delay variation reduction when compared to adders of the literature. Therefore this technique can be used to control variance of critical paths delay and efficiently meet timing constraints and thus improve timing yield. Experiments conducted span several values of intra-die and die-to-die variance, so that cases of practical interest for various nanoscale technologies are covered.12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools, DSD 2009, 27-29 August 2009, Patras, Greece; 01/2009
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ABSTRACT: The purpose of this paper is to model timing of digital circuits by determining dependencies between the logical depth of standard cells in digital circuit and variation margins applied during timing analysis. The simulation results for the cells used in clock tree are presented.
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