Cycle life testing of smart power switches requires significant hardware effort to provide the required ohmic-inductive load patterns. A new reliability test system for research purposes is therefore introduced that generates arbitrary current waveforms to emulate inductive switching behavior. This allows flexible cycle stress testing of integrated power switches under arbitrary application conditions. The current drivers of the proposed "ARCTIS" test system are protected from thermal overload in case of failure of a stressed device using a combination of case temperature sensing and a thermal equivalent circuit. Therefore the power MOSFETs in the output stage may be utilized to the limits of their dynamical safe operating area. All devices under test are continuously monitored for short circuit and open load failures. The respective waveforms and failure events are digitally recorded by the PXI-based control system to obtain a statistical basis for the evaluation of cycle life time.
"Demands on the reliability of these devices are already high, but nevertheless they continue increasing for the sake of the passengers safety. To define safe and reliable operating conditions, numerous resource-consuming measurements and lifetime tests are necessary (Glavanovics et al. (2007)), because low failure rates, expressed in parts per million (ppm) quantiles, under certain stress test conditions are desired. High specification requests, like 1ppm quantiles at 1e6 Cycles to Failure (CTF), result therefore in long testing times. "
[Show abstract][Hide abstract] ABSTRACT: The problem of contemporary semiconductor reliability testing is twofold: on one hand demands on the device lifetime increase steadily implying longer testing times and on the other hand resources are limited (devices, testing time, ...). Therefore it seems unavoidable to apply advanced statistical methods to gain a reliable lifetime model. To increase the model quality significantly, we propose a combination of optimal Design of Experiments (DoE) and Bayesian statistical modeling. Optimal DoE ensures that the data for the model contain as much information as possible, whereas Bayesian modeling provides the possibility to include available prior information. With this approach resources can be saved because lifetime testing can be reduced to a necessary minimum.
[Show abstract][Hide abstract] ABSTRACT: References  Bluder, O. and Waukmann, A.: Bayesian lifetime modeling for power semiconductor devices. World Congress on Engineering and Computer Science 2009, pp.826 -831, Newswood Limited, 2009  Diebolt, J. and Robert, Ch. P.: Estimation of finite mixture distributions through Bayesian sampling. approach to model selection in hierarchical mixture-of-experts architectures. Neural Networks, 10(2), pp. 231-241, 1997.
[Show abstract][Hide abstract] ABSTRACT: In this article the failure behavior of DMOS-switches under power-cycle stress is shown to be dominated by thermo-mechanical deformation of the metallization. The failure evolves without a significant influence from electromigration stress.
Solid State Device Research Conference, 2007. ESSDERC 2007. 37th European; 10/2007
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