Full copper wiring in a sub-0.25 μm CMOS ULSI technology
ABSTRACT We present the first fully integrated ULSI CMOS/copper
interconnect technology. Up to 6 Cu wiring levels are built at minimum
metal-contacted pitch of 0.63 μm, with W local-interconnect and
contact levels and a polycontacted pitch of 0.81 μm, on a
fully-scaled sub 0.25 μm, 1.8 V CMOS technology. The Cu wiring has
advantages of significantly lower resistance, higher allowed current
density, and increased scalability, relative to comparable Ti/Al(Cu)
wiring. These benefits in turn have enabled the scaling of pitch and
thickness, from reduced-capacitance, high-density lower levels to low RC
global wiring levels, consistent with high-performance and high-density
needs. The integrated Cu hardware was evaluated according to a
comprehensive set of yield, reliability, and stress tests. This included
fully functional, high-density 288 K SRAM chips which were packaged into
product modules and successfully tested for reliability. Overall, we
find the results for full Cu wiring meet or exceed the standards set by
our Al(Cu)/W-stud technology
Conference Paper: VLSI interconnect process integration[Show abstract] [Hide abstract]
ABSTRACT: This paper describes VLSI interconnect process integration with respect to ULSI scaling. Both resistivity and capacitance are key factors for materials used in the interconnect process integration. In order to reduce parasitic resistances of sub-quarter micron CMOS transistors, salicide technologies have been developed for gate and source/drain electrodes. Copper interconnects and low-k interlayer dielectrics, in conjunction with CMP planarization, have been developed to reduce RC delay for future scaled ULSIsSolid-State and Integrated Circuit Technology, 1998. Proceedings. 1998 5th International Conference on; 02/1998
Article: Delamination in patterned films[Show abstract] [Hide abstract]
ABSTRACT: When the dielectric constant of an insulator in an interconnect is reduced, mechanical properties are often compromised, giving rise to significant challenges in interconnect integration and reliability. Due to low adhesion of the dielectric an interfacial crack may occur during fabrication and testing. To understand the effect of interconnect structure, an interfacial fracture mechanics model has been analyzed for patterned films undergoing a typical thermal excursion during the integration process. It is found that the underlayer pattern generates a driving force for delamination and changes the mode mixity of the delamination. The implications of our findings to interconnect processes and reliability testing have been discussed.International Journal of Solids and Structures 01/2007; 44(6):1706-1718. · 2.04 Impact Factor
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ABSTRACT: Three novel CSP pad designs in a 0.18mum CMOS image sensor Cu interconnect technology were analyzed for use with a wafer level CSP (WLCSP) package. The CSP pad designs used various combinations of available aluminum and tungsten interconnect levels in order to improve the cross-sectional area without increasing the total stack height of the Cu interconnect technology. It was found that by increasing the cross-sectional area of the CSP pads the T-connections formed in the CSP process had improved (tighter) resistance distributions01/2006;
Full Copper Wiring in a Sub-0.25 pm CMOS ULSI Technology
D. Edelstein*, J. Heidenreich, R. Goldblatt, W. Cote, C. Uzoh, N. Lustig, P. Roper, T. McDevittt, W. Motsifft,
A. Simon, J. Dukovic, R. Wachnik, H. Rathore, R. Schulz , L. Su, S. Lucet, and J. Slatteryt
IBM Semiconductor Research and Development Centel; Hopewell Junction, NY 12533
tIBM Microelectronics, Essex Junction, VT 05452
“Phone: (91 4) 945-3051: FM: (91 4) 945-401 5: E-mail: firstname.lastname@example.org
We present the first fully integrated ULSI CMOS/
copper interconnect technology. Up to 6 Cu wiring levels
are built at minimum metal-contacted pitch of 0.63 pm,
with W local-interconnect and contact levels and a poly-
contacted pitch of 0.81 pm, on a fully-scaled sub
0.25 pm, 1.8V CMOS technology. The Cu wiring has
advantages of significantly lower resistance, higher
allowed current density, and increased scalability, relative
to comparable Ti/Al(Cu) wiring’. These benefits in turn
have enabled the scaling of pitch and thickness, from
reduced-capacitance, high-density lower levels to low-
RC global wiring levels, consistent with high-perfor-
mance and high-density needs. The integrated Cu
hardware was evaluated according to a comprehensive
set of yield, reliability, and stress tests. This included
llly functional, high-density 288K SRAM chips which
were packaged into product modules and successfully
tested for reliability. Overall, we find the results for full
Cu wiring meet or exceed the standards set by our
The key parameters of this technology are summa-
rized in Table along with comparable values for the
0.25 pm technology that is currently in production.
Figure 1 shows an SEM section of a device contacted at
mini“ pitch. Figures 2 and 3 show device current-
drive and subthreshold performance for WET and PFET
devices built with this technology. Aggressive vertical
and lateral dopant engineering leads to excellent short-
channel effects and current-drive characteristics, even
down to below 0.10 pm effective channel lengthz. The
aggressive pitches and use of W damascene local
interconnects allow for a 6-transistor SRAM cell size of
only 6.8 pmz, as described in ref. 4. As indicated in Table
I, metal pitches range from 0.63 to 0.81 pm for up to 6
levels, with optional 2x-scaled pitcWthickness at M5 and
M6 for very-low RC applications.
Cu Interconnect Technology
The Cu dual-damascene process5 (inlaid, planarized
metal in vidine insulator cavity) is employed for the
6-level builds shown in fig. 4 (all t h i n wires), fig. 5 (2x-
scaled low-RC 5* and 6* levels), and fig. 6 (lx- and 2x-
scaled via-chains). This is accomplished by chem-mech
polishing of an electrolytically-plated Cu fill. The electro-
plated Cu process has exceptional pattern-filling capability,
as indicated by fig. 7. This TEM section shows an 0.2 pn
reentrant profile in polyimide, filled in a void-free manner
with plated Cu. The plated Cu consistently shows a 1.8
pn-cm resistivity, and the composite interconnects (with
liner) range from 1.9 to 2.2 @-cm for thicker or minimum
lines, respectively; this is a 40-45% drop fi-om comparable
TUAl(Cu)/Ti lines. Figure 8 shows Cu vs. Al(Cu) 0.63 pm
pitch M1 wire resistances; here the Cu was scaled such
that R is reduced by 25% and C by 15%. The Cu via
contact resistances are about half that of the Al(Cu)/W-
studs, as shown in fig. 9 for long via-chains from several
wafer lots. Figure 10 shows wafer lot yields for large M3
mazes at minimum pitch, built on all the lower wiring
levels. The good yields indicate a robustness of the
integration process against intra- and interlevel defects.
The integrity of the CMOS/Cu integration was
evaluated using key reliability and stress tests on a
variety of structures, circuits, and packaged modules. In
many cases, control samples with Al(Cu)/W wiring on
identical chips were included. Table I1 shows product
functional stress results on 288K SRAM chips with all
Cu wiring @om two populations of hardware) that were
packaged into wirebond modules. The SRAMs were of
the minimum 6.8 pmz cell design, embedded within and
diced out of larger test chips. All SRAM chips were fully
functicnal after passing high voltage screening (except as
noted) prior to the stresses shown. The voltage-screened
Cu parts showed only one fail after extended functional
stress at 2.7V/14OoC operation and no fails after 200
thermal cycles. These results showed statistically equiva-
lent reliability to the Al(Cu) hardware that was run in
parallel. This, we believe, is the first report of a CMOS/
Cu-wiring technology carried through product-like chip,
package, and burn-in conditions.
Test-chips and SRAMs with CU last-metal levels were
also assembled into C4 “flip-chip” modules, and passed
thermal cycling (T/C), “highly-accelerated stress-test”
(HAST), temperature/humidity/bias (T/H/l3), and SRAM
0-7803-410&7/97/$10.00 0 1997 IEEE
functional tests. In all of the module types tested, the
MC4 modules had equivalent reliability (Nso, 0) to the
Al(Cu)/C4 controls, where the C4 fatigue life is the
limiting factor. Fig. 11 shows one of the C4 solder balls on
Cu wiring after 10 reflow cycles to 375"C, to test for fails
by Cu(Sn) intermetallic formation in the wiring; no such
fails have been found in any of the stressed hardware.
The potential for Cu contamination of the MOS
devices was investigated aggressively, for example with
high temp/bias stresses on devices with large-area
exposure to the Cu wires. Fig. 12 shows leakage data
from 236K pm2 p+-poly/gate-oddiffusion capacitors after
stress, showing no Cu vs. AI(Cu) anomalies. Large
numbers of several device types were stressed for 300
hrs. at 14O-29O0C, with M1 biases from -2 to -5OV (to
drive any Cu' ions towards the gates or junctions).
Devices included large-area, plate or fingered diffusion
capacitors, NFETS, and PFETS under large-area Cu M1
plates or fingers. Some structures had intentional line/
stud misalignment, in an attempt to promote defects.
Figure 13 shows an example of Cu plateNFET junction
leakage vs. time at 3OV/25O0C stress, showing no shifts.
In all, 720 chips from several wafer lots were tested, and
no fails by Cu poisoning were found.
The Cu wiring itself was also stress-tested extensively.
Intrinsic Cu reliability, such as electromigration resis-
tance, was confirmed to be orders of magnitude better
than for TilAl(Cu)/Ti, as reported previouslys. Figure 14
shows electromigration data for the worst-case situation
tested here: 0.3 pm single-damascene M1 lines on W-
studs, at 295"C, and with 2.5MA/cm2 stress current. The
T,, lifetime is >1 O O x longer for Cu than for our best Til
Al(Cu)/Ti lines. The Cu lifetime improvement is even
greater for the other line levels, and at lower temperatures
(higher Cu activation energy), and projects to several
orders of magnitude longer lifetimes for Cu at chip-use
conditions. This supports a much higher current density
spec and underpins the extendability of our Cu wiring for
future pitches, higher performance, and scaling of line
cross-sections to minimize capacitance and crosstalk.
Also, high-current needs for the upper wiring levels, such
as DC power distribution, off-chip YO, etc. can be done
at greatly increased wiring density relative to Al(Cu).
Another intrinsic wiring reliability issue is stress-
migration, or the slow formation of voids in fine lines
under tensile stress at chip operating temperatures. Figure
15 shows resistance vs. square root of time (to show any
straight-line diffusive response) for 20 chips each of Cu
vs. Al(Cu) in specialized test structures. These structures
simulate high-fanout from a single contact stud with 0.3
pm lines, and respond more strongly than typical chip
wiring to stress-voiding. Parts were stored at 225°C
(predicted maximum stress-migration temp) for thou-
sands of hours, with periodic readouts. The upper traces
show large resistance rises and scatter for Al(Cu) lines in
this structure; this typical response has been correlated
with stress-voiding. In sharp contrast, there is no rise or
scatter at all in the Cu lines, even after 5000 hrs.; the Cu
resistance actually decreases slightly, due to annealing.
Post-analysis confumed no stress-voiding in the Cu lines.
This Cu benefit is especially important for the future, as
stress-voiding is projected to be more severe for decreas-
"Extrinsic" reliability that relates to the integration,
such as corrosion, defects, or weak interfaces, was
evaluated by extended T/WB and T/C stresses on 3- and
6-level Cu hardware. For example, T/H/B stress was
done on 100 modules for 1000 hrs. at 85"C/85% r.h./
3.6V, with no fails found in any of the devices tested. An
example of T/C stress results is shown in table 111, where
1 1,400 Cu multilevel line/stud structures were subjected
to 1,550 shallow and deep thermal cycles, with no fails.
The T/H/I3 results also found no fails for Al(Cu) or Cu
hardware after 1000 hrs. at 85"C/81% r.h./3.6V. These
defect-sensitive, no-fail results meet (at least) the expec-
tations for the AI(Cu)/W wiring, and indicate a lack of
significant weaknesses in the Cu integration scheme.
In summary, a full copper/CMOS integrated circuit
technology is presented. The key integration and reliabil-
ity issues are addressed, with results that demonstrate the
feasibility of copper interconnects for CMOS ULSI
The authors are greatly indebted to their many col-
leagues in the Advanced Semiconductor Technology
Center, the Reliability Engineering, and Physical Charac-
terization groups, who made very significant and excel-
lent contributions to this work.
1. D. Edelstein, Proc. VMIC, 12, 301 (1995).
2. L. S u et al., Proc. IEEE VLSI Tech. Symp., 12 (1996).
3. L. Gwennap, Microprocessor Report, 11, 14 (1997).
4. S. Subbanna et al., Proc. IEEE IEDM, 275 (1996).
5. C.-K. Hu et al., Proc. MRS Symp. on VLSI, 5, 369 (1990); B. Luther et
al., Proc. VMIC, 10, 15 (1994); D. Edelstein, Proc. ECS Mtg., 96-2,
6. c.-K. Hu, et al., IBM J. Res. Devel., 39, 465 (1 995).
110 voltage (max)
Gate length (drawn)
Channel length (effective)
Gate ox. thickness
# Metal lavers
MI contacted pitch
M2-M6 cont. pitch"
SRAM cell size
*opIionai Zx-scaled tbi&ness/ptcb MS, M6 for low-RC
Table 1. CMOS Technology parameters,
0.63 p n
figure 5. SEM of 6-level Cu build with 2x-scaled, low-RC M5 and M6.
figure 7. SEM of 0.20 pm MOSFET with minimum-pitch contacts.
Lefi=0.092 p m
2 ' 0.6
l ? s
0 . 0
Figure 6. SEM views (same magnification) of lx- (inset) and 2x-
scaled dual-damascene intertwined via-chains*
Drain Volta#s, Vds (v)
Figure 2. ld-Vds characteristics of NFET and PFET devices (IV,,I=O-
1.8V, 0.3V steps).
figure 7. TEM of electroplated Cu fill in 0.2pm, 4:1 reentrant
polyimide test via.
Gllle VOltlpe, Vds (v)
Figure 3. Subthreshold characteristics of NFET and PFET devices.
figure 4. SEM of 6-level thin-wire Cu build. M1 Cu (transverse) is
connected by W-studs to W local-interconnects.
Figure 8. Sheet-resistance data by wafer for M1 Cu vs. AI(Cu)
Figure 9. Resistancellink for Cu vs AI(Cu)/W via chains.
P+ Poly CG Large Area Dff: A=235,616pm2, P=Zl84pm (PFETPAD 6,7)
I I I
Figure 10. Wafer lot yield trend for large-area, minimum-pitch M3
mazes in multilevel Cu builds.
2.3V/1 OO"C15 hrs
2.7V/014"C/I 44 hrs
2.7VlO1 4"C15000 hrs
0-1 25°C Thermal Cycle 20X
-40-1 50°C TIC 20X
-40-1 50°C TIC 200X
+This chip was not voltage-screened
Group 1 Fails
Group 2 Fails
Table I/, Functional stress results on 288K SRAM modules with Cu
Figure I f . SEM section of C4 Pb(Sn) solder-ball on Cu wiring after
10 reflow cycles to 375°C.
T O H n
Temp = z 5 m
.- 13 n n
sx-s vonage 01)
Figure 13. NFETlCu device substrate-source (Sx-S) junction
leakage after time intervals shown at 250°C/30V stress.
StrSEs lime (Hrs)
Figure 14. Electromigration data at 295"C, 2.5 MNcm* for Cu vs.
AI(Cu) 0.3 vm multilevel lines.
Stress = 225°C
3000 4000 500C
Figure 15. Stress-migration test structure resistance vs. square-
root time for Cu vs. AI(Cu) 0.3 pm lines (20 chips each).
-65-1 50°C TIC 1 O O O X
-1 65-1 80°C TIC 350X
-1 60400°C T/C 200X
i# Cu Fails
Table 111. Thermal-cycle stress results on 3- and 6-level Cu via chains.