Conference Paper

Full copper wiring in a sub-0.25 mu m CMOS ULSI technology

Semicond. Res. & Dev. Center, IBM Corp., Hopewell Junction, NY
DOI: 10.1109/IEDM.1997.650496 Conference: Electron Devices Meeting, 1997. IEDM '97. Technical Digest., International
Source: IEEE Xplore

ABSTRACT We present the first fully integrated ULSI CMOS/copper
interconnect technology. Up to 6 Cu wiring levels are built at minimum
metal-contacted pitch of 0.63 μm, with W local-interconnect and
contact levels and a polycontacted pitch of 0.81 μm, on a
fully-scaled sub 0.25 μm, 1.8 V CMOS technology. The Cu wiring has
advantages of significantly lower resistance, higher allowed current
density, and increased scalability, relative to comparable Ti/Al(Cu)
wiring. These benefits in turn have enabled the scaling of pitch and
thickness, from reduced-capacitance, high-density lower levels to low RC
global wiring levels, consistent with high-performance and high-density
needs. The integrated Cu hardware was evaluated according to a
comprehensive set of yield, reliability, and stress tests. This included
fully functional, high-density 288 K SRAM chips which were packaged into
product modules and successfully tested for reliability. Overall, we
find the results for full Cu wiring meet or exceed the standards set by
our Al(Cu)/W-stud technology

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Available from: Andrew Simon, Jan 11, 2015
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    • "OPPER has frequently replaced aluminum for interconnect applications in semiconductor devices due to its higher electrical conductivity, increased electromigration resistance , and better thermal conductivity [1], [2]. Electrochemical deposition (ECD) of copper has been demonstrated as one of the best methods to be adopted for high-performance logic devices using dual damascene technology and for power devices using pattern plating technology [3]–[5]. The recrystallization of ECD Cu at room temperature, which is termed self-annealing, is a very distinct phenomenon [6]–[10]. "
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    ABSTRACT: Electroplated copper films are known to change their microstructure due to the self-annealing effect. The self-annealing effect of electroplated copper films was investigated by measuring the time dependence of the film stress and sheet resistance for different layer thicknesses between 1.5 and 20 ??m. While the sheet resistance was found to decrease as time elapsed, a size-dependent change in film stress was observed. Films with the thickness of 5 ??m and below decrease in stress, while thicker films initially reveal an increase in film stress followed by a stress relaxation at a later stage. This behavior is explained by the superposition of grain growth and grain-size-dependent yielding.
    IEEE Transactions on Device and Materials Reliability 04/2010; 10(1-10):47 - 54. DOI:10.1109/TDMR.2009.2032768 · 1.89 Impact Factor
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    • "RC delay model, in which it was assumed that crosstalk noise is due to capacitive coupling between adjacent wires. Due to shrinking in technology [1] "
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    Signal Propagation on Interconnects, 2007. SPI 2007. IEEE Workshop on; 06/2007
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    • "Digital Object Identifier 10.1109/TED.2006.872095 devices [4]–[7]. Further reductions in interline capacitance are required for 65-nm-node interconnects achieved through the use of porous materials (k < 2.7). "
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    ABSTRACT: Robust porous low-k/Cu interconnects have been developed for 65-nm-node ultralarge-scale integrations (ULSIs) with 180-nm/200-nm pitched lines and 100-nm diameter vias in a single damascene architecture. A porous plasma-enhanced chemical vapor deposition (PECVD)-SiOCH film (k=2.6) with subnanometer pores is introduced into the intermetal dielectrics on the interlayer dielectrics of a rigid PECVD-SiOCH film (k=2.9). This porous-on-rigid hybrid SiOCH structure achieves a 35% reduction in interline capacitance per grid in the 65-nm-node interconnect compared to that in a 90-nm-node interconnect with a fully rigid SiOCH. A via resistance of 9.7 Ω was obtained in 100-nm diameter vias. Interconnect reliability, such as electromigration, and stress-induced voiding were retained with interface modification technologies. One of the key breakthroughs was a special liner technique to maintain dielectric reliability between the narrow-pitched lines. The porous surface on the trench-etched sidewall was covered with an ultrathin plasma-polymerized benzocyclobuten liner (k=2.7), thus enhancing interline time-dependent dielectric breakdown reliability. The introduction of a porous material and the control of the sidewall are essential for 65-nm-node and beyond scaled-down ULSIs to ensure high levels of reliability.
    IEEE Transactions on Electron Devices 06/2006; 53(5-53):1169 - 1179. DOI:10.1109/TED.2006.872095 · 2.47 Impact Factor
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