RAMPSoCVM: Runtime Support and Hardware Virtualization for a Runtime Adaptive MPSoC
ABSTRACT Virtualizing complex hardware, such as heterogeneous multiprocessor systems, enables developers to use standard Application Programming Interfaces (APIs) for application integration. Especially, the supply of an Operating System (OS) is well appreciated since many features such as drivers, the runtime environment and scheduling mechanisms are available and well established. For this purpose, Embedded Linux was used as basis OS and extended in order to be able to manage a Runtime Adaptive Multi-Processor System-on-Chip (RAMPSoC) and to provide the standard Message Passing Interface (MPI). This paper describes the adaptation of the Linux kernel supporting MPI with runtime libraries as well as the integration of the software/hardware drivers which supply the message transfer over a reconfigurable and heterogeneous Network-on-Chip (NoC).
SourceAvailable from: Suhaib Fahmy[Show abstract] [Hide abstract]
ABSTRACT: Emerging hybrid reconfigurable platforms tightly couple capable processors with high performance reconfigurable fabrics. This promises to move the focus of reconfigurable computing systems from static accelerators to a more software oriented view, where reconfiguration is a key enabler for exploiting the available resources. This requires a revised look at how to manage the execution of such hardware tasks within a processor-based system, and in doing so, how to virtualize the resources to ensure isolation and predictability. This view is further supported by trends towards amalgamation of computation in the automotive and avionics domains, where such properties are essential to overall system reliability. We present the virtualized execution and management of software and hardware tasks using a microkernel-based hypervisor running on a commercial hybrid computing platform (the Xilinx Zynq). The CODEZERO hypervisor has been modified to leverage the capabilities of the FPGA fabric, with support for discrete hardware accelerators, dynamically reconfigurable regions, and regions of virtual fabric. We characterise the communication overheads in such a hybrid system to motivate the importance of lean management, before quantifying the context switch overhead of the hypervisor approach. We then compare the resulting idle time for a standard Linux implementation and the proposed hypervisor method, showing two orders of magnitude improved performance with the hypervisor.Journal of Signal Processing Systems 10/2014; 77(1-2). DOI:10.1007/s11265-014-0884-1 · 0.56 Impact Factor
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ABSTRACT: Virtualization is generally adopted in server and desktop environments to provide for fault tolerance, resource management, and energy efficiency. Virtualization enables parallel execution of multiple operating systems (OSs) while sharing the hardware resources. Virtualization was previously not deemed as feasible technology for mobile and embedded devices due to their limited processing and memory resource. However, the enterprises are advocating Bring Your Own Device (BYOD) applications that enable co-existence of heterogeneous OSs on a single mobile device. Moreover, embedded device require virtualization for logical isolation of secure and general purpose OSs on single device. In this paper we investigate the processor architectures in the mobile and embedded space while examining their formal virtualizabilty. We also compare the virtualization solutions enabling coexistence of multiple OSs in Multicore Processor System-on-Chip (MPSoC) mobile and embedded systems. We advocate that virtualization is necessary to manage resource in MPSoC designs and to enable BYOD, security, and logical isolation use cases.International Conference of Global Network for Innovative Technology (IGNITE-2014), Penang, Malaysia; 12/2014
Conference Paper: uVMP: Virtualizable multi-core platform[Show abstract] [Hide abstract]
ABSTRACT: This paper aims to show the design and prototyping of a multi-core platform that includes hardware resources to multi-core embedded processor virtualization. The virtualization process may configure the cores' address space and the association of cores to create independents groups of cores inside the platform. The platform was prototyped and validated through simulation of applications devoted to explore its main characteristics. The results have proven that the proposed architecture is useful to run concurrent applications, demanding different memory organization. The proposed architecture can achieve 67 MHz in an FPGA implementation running simultaneously eight computing tasks and one management task. Application execution shows that the proposed architecture is able to provide 94,9 MIPS (Millions of Instruction Per Second) of measured performance.Informatica (CLEI), 2012 XXXVIII Conferencia Latinoamericana En; 01/2012