Virtualizing complex hardware, such as heterogeneous multiprocessor systems, enables developers to use standard Application Programming Interfaces (APIs) for application integration. Especially, the supply of an Operating System (OS) is well appreciated since many features such as drivers, the runtime environment and scheduling mechanisms are available and well established. For this purpose, Embedded Linux was used as basis OS and extended in order to be able to manage a Runtime Adaptive Multi-Processor System-on-Chip (RAMPSoC) and to provide the standard Message Passing Interface (MPI). This paper describes the adaptation of the Linux kernel supporting MPI with runtime libraries as well as the integration of the software/hardware drivers which supply the message transfer over a reconfigurable and heterogeneous Network-on-Chip (NoC).
"Several Linux extensions have also been proposed to support reconfigurable hardware , . RAMPSoCVM  provides runtime support and hardware virtualization for an SoC through APIs added to Embedded Linux to provide a standard message passing interface. "
[Show abstract][Hide abstract] ABSTRACT: Reconﬁgurable architectures have found use in a wide range of application domains, but mostly as static accelerators for computationally intensive functions. Commodity computing adoption has not taken off due primarily to design complexity challenges. Yet reconﬁgurable architectures offer signiﬁcant advantages in terms of sharing hardware between distinct isolated tasks, under tight time constraints. Trends towards amalgamation of computing resources in the automotive and aviation domains have so far been limited to non-critical systems, because processor approaches suffer from a lack of predictability and isolation. Hybrid reconﬁgurable platforms may provide a promising solution to this, by allowing physically isolated access to hardware resources, and support for computationally demanding applications, but with improved programmability and management. We propose virtualized execution and management of software and hardware tasks using a microkernel-based hypervisor running on a commercial hybrid computing platform (the Xilinx Zynq). We demonstrate a framework based on the CODEZERO hypervisor, which has been modiﬁed to leverage the capabilities of the FPGA fabric. It supports discrete hardware accelerators, dynamically reconﬁgurable regions, and regions of virtual fabric, allowing for application isolation and simpler use of hardware resources. A case study demonstrating multiple independent (and isolated) software and hardware tasks is presented.
IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), http://www.ntu.edu.sg/home/sfahmy/files/papers/asap2013-khoa.pdf; 01/2013
[Show abstract][Hide abstract] ABSTRACT: Dynamic reconfiguration of hardware resources is increasingly used in applications as a way to increase performances, resources integration or energy efficiency. As this evolution induces a change of the application execution paradigm, various tools have been set up to develop and manage these applications. But most do not allow direct re-use of legacy code, needing adaptation to match the provided environment. Moreover, partial reconfiguration is only at its early stages, and lacks easy ways of handling. We propose a design methodology and a runtime environment bringing fast integration of legacy hardware accelerators for partial and dynamic reconfigurable hardware architectures. Thanks to it, applications making use of dynamic hardware can be run directly on an Embedded Linux without noticing the reconfiguration flow. Moreover, our design methodology allows providing various implementations of a computation kernel, including both hardware and software ones. The implementation can then be chosen at execution time depending on available resources. In this article, we introduce the generic IP interface description making the reuse process possible. Furthermore, we present the results of a sample application running on our platform using software and hardware implementations. For hardware implementations, we obtain reconfiguration overhead as low as 0.16% of the total kernel execution time.
Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), 2012 7th International Workshop on; 07/2012
[Show abstract][Hide abstract] ABSTRACT: This paper aims to show the design and prototyping of a multi-core platform that includes hardware resources to multi-core embedded processor virtualization. The virtualization process may configure the cores' address space and the association of cores to create independents groups of cores inside the platform. The platform was prototyped and validated through simulation of applications devoted to explore its main characteristics. The results have proven that the proposed architecture is useful to run concurrent applications, demanding different memory organization. The proposed architecture can achieve 67 MHz in an FPGA implementation running simultaneously eight computing tasks and one management task. Application execution shows that the proposed architecture is able to provide 94,9 MIPS (Millions of Instruction Per Second) of measured performance.
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