This paper is a postprint of a paper submitted to and accepted for publication in IET Electrical Systems in Transportation and
is subject to Institution of Engineering and Technology Copyright. The copy of record is available at IET Digital Library.
Superconducting fault current limiter application in a
power-dense marine electrical system
S.M. Blair*, C.D. Booth*, I.M. Elders*, N.K. Singh*1, G.M. Burt*, J. McCarthy†
*Institute for Energy and Environment, University of Strathclyde, Glasgow, UK,
†Rolls-Royce Marine Electrical Systems, Portsmouth, UK, email@example.com
Keywords: Fault level, marine electrical systems, protection and control, superconducting fault
Power-dense, low-voltage marine electrical systems have the potential for extremely high fault
currents. Superconducting fault current limiters (SFCLs) have been of interest for many years and
offer an effective method for reducing fault currents. This is very attractive in a marine vessel in terms
of the benefits arising from reductions in switchgear rating (and consequently size, weight and cost)
and damage at the point of fault. However, there are a number of issues that must be considered prior
to installation of any SFCL device(s), particularly in the context of marine applications. Accordingly,
this paper analyses several such issues, including: location and resistance sizing of SFCLs; the
potential effects of an SFCL on system voltage, power and frequency; and practical application issues
such as the potential impact of transients such as transformer inrush. Simulations based upon an actual
vessel are used to illustrate discussions and support assertions. It is shown that SFCLs, even with
relatively small impedances, are highly effective at reducing prospective fault currents; the impact
that higher resistance values has on fault current reduction and maintaining the system voltage for
other non-faulted elements of the system is also presented and it is shown that higher resistance values
1 Dr Nand Singh is now with Mott MacDonald Ltd., Croydon, CR0 2EE, U.K
are desirable in many cases. It is demonstrated that the exact nature of the SFCL application will
depend significantly on the vessel’s electrical topology, the fault current contribution of each of the
generators, and the properties of the SFCL device, such as size, weight, critical current value and
Superconducting fault current limiters (SFCLs) have the potential to facilitate highly power-dense,
low-voltage electrical systems. This applies particularly to marine electrical systems, in which
electrical power requirements for propulsion, auxiliary systems and other loads are increasing , .
The necessary generation capacity at a given voltage level may result in fault currents such that
procurement of adequately rated switchgear is prohibitively expensive, or impossible; furthermore,
there are increased safety concerns when fault currents become excessively high. As will be
demonstrated later in this paper, fault currents well in excess of 200kA peak can be encountered. The
preference for use of low voltage marine electrical systems is driven by the costs of increased
insulation associated with higher voltages, employing crew with particular operating qualifications
and increasingly stringent safety regulations. Restriction of fault currents by a means that does not add
operational constraints during non-fault conditions is therefore very attractive , , .
Resistive SFCLs operate on the principle that passing a current, which is greater than the
superconductor’s critical current, Ic, through a superconducting wire causes a small amount of ohmic
heating and, when the wire temperature increases sufficiently, results in the superconductor
“quenching”, and transitioning to a resistive state , , . Hence, there are virtually no losses in
the SFCL during normal operation (ignoring power losses associated with the operation of the
cryogenic system), yet an SFCL intrinsically inserts impedance into the fault current path during a
fault, as long as its transition threshold conditions are satisfied. SFCLs are not restricted to a single
current limiting operation, but usually require a recovery period after operation, ranging from several
seconds  to several minutes , during which the element is cooled until it returns to its
superconducting state. SFCLs are therefore a much more favourable solution to addressing high fault
levels than traditional solutions such as fault current limiting reactors, Is-limiters and reduced
electrical network interconnection , all of which have a number of operational and safety-related
disadvantages , . Several types of SFCL have been proposed, some of which do not require
recovery , but for simplicity this paper focuses on the application of resistive SFCLs. An example
of a resistive SFCL device is illustrated Figure 1.
Figure 1: Resistive SFCL device design, courtesy of Applied Superconductor Ltd.
This paper presents a detailed study of the impact of SFCLs on fault currents in a marine electrical
network. The vessel chosen for the case study is an offshore anchor handling/supply vessel with a
relatively large installed generation capacity. The modelling approach, including modelling of the
resistive SFCL device, and analysis of prospective fault current levels, are described in Section 2.
Section 3 compares the effectiveness of limiting fault current using SFCLs with a variety of resistance
values and considers the impact of locating the devices at different locations within the power system.
The effects of SFCLs on voltage, power and frequency and other practical application concerns are
explored in Section 4. Based on the results presented, the paper concludes with a summary of the
various aspects that must be considered prior to the application of SFCLs in marine vessels, and
suggestions for further investigation are made.
2 Case study marine system
The vessel under consideration has six synchronous diesel generators, four 2.1MW and two 4MW
units, as presented in the electrical system diagram in Figure 2. The 4MW generators are associated
with local propulsion and thruster motors; they are also connected to the main switchboard and are
therefore capable of supplying other non-propulsive loads. As depicted in Figure 2, the system can be
divided into two similar subsystems – connected by bus-tie circuit breakers – with loads evenly
distributed between them. Auxiliary loads are connected to both 690V and 230V switchboards.
Figure 2: Marine electrical system
2.1 Marine model and analysis method
The electrical system modelling has been carried out using PSCAD/EMTDC . As is typical of AC
marine electrical systems, it is an isolated (unearthed) system and has a nominal frequency of 60Hz.
Two types of synchronous generators have been used in the modelling of system; relevant generator
data is provided in the Appendix. The generators’ excitation control systems have been implemented
based on IEEE standard model AC1A , using the default parameters, and a standard governor
control system provided in PSCAD has been used. A pi-equivalent model of cables has been used
during this investigation, with resistance of 83.9µΩ/m and inductive reactance of 142.5µΩ/m (this
data was supplied by the project’s industrial partner). Cable lengths are illustrated in Figure 3.
Standard PSCAD transformer components have been used to model system transformers; the
transformers do not play a significant role in the studies presented.
Figure 3: Fault locations, SFCL locations (A, B, C or D), and cable lengths
Figure 2 shows presence of both static and dynamic loads. However, it can be seen that motors are
connected through power electronic converters capable of providing a current control scheme.
Therefore, with a current controlled scheme in place, pre- and post-fault currents of the drive systems
remain unchanged, i.e., load current is controlled to 1pu which allows motoring load to be modelled
as static load, leading to simplified modelling and shorter simulation times. The motor-generator
arrangement is assumed to be disconnected from the system; the 230V loads connected to the main
switchboard are supplied via the parallel transformer. This assumption is valid for fault level studies
because the motor is convertor-interfaced and would not contribute significantly to the fault current.
The emergency generator, emergency switchboard, and shore connection are not considered in this
This paper considers the worst case scenario of three-phase faults, applied at the locations of interest
(shown in Figure 3) with a negligible fault resistance value. Fault currents are calculated by PSCAD
using the EMTDC simulation engine . It is assumed that the selected circuit breakers are capable of
closing onto and breaking the maximum prospective fault current supplied by only one “half” of the
available generation. For this reason the bus-tie (at location A in Figure 3) must be open when all
generation is operational unless fault current limitation is present.
2.2 Resistive SFCL model
In order to accurately examine the dynamics and operational characteristics of a marine electrical
system incorporating an SFCL – such as the peak make fault current (the maximum possible
instantaneous value of the prospective short-circuit current ) – the resistance in each phase of the
SFCL is modelled independently. An exponential SFCL model (effectively a refined version of the
models presented in ,  and ) is used to approximate the development of resistance; this
process is triggered when the instantaneous current in each phase first exceeds the critical current
value, Ic . Hence, the SFCL model intrinsically reacts to current magnitudes in each individual
phase and does not have to be configured to operate at a specific time; this is a valuable refinement
when compared to other models (such as , , ,  and ), which may tend to
overestimate the reduction in peak make fault current and lead to inaccurate transient results until the
final SFCL resistance value is reached. The model used in this study is effective at estimating the
peak make fault current reduction, yet it avoids the complexities of thermo-electric models such as
those described in ,  and .
Equation (1) describes the model used in the studies presented in this paper, where: R0 is the
maximum SFCL resistance value; τ is the time constant which determines how quickly the SFCL
reaches R0; and iSFCL(t) is the instantaneous phase current in the SFCL. The value of τ is assumed to be
10ms, which implies that the SFCL phase resistance reaches approximately 80% of R0 within the first
cycle (depending on the point during the first cycle when Ic is reached). This may be a conservative
estimate for τ; in reality the transition time is also dependent on the fault current magnitude ) but,
for sufficiently large values of R0, a more optimistic value such as 1ms only makes a small difference
in terms of reducing peak make current. In either case, the SFCL resistance is sufficient to
significantly limit the first peak of fault current.
????? ? =
0, ?????? ????? ? ≥ ??
?0 1 − ?
? , ????? ????? ? ≥ ??
Equation 1: SFCL resistance model, calculated independently for each phase
Ic is selected to be approximately 2pu of the maximum load current that can pass through the SFCL in
each scenario. The value of Ic will slightly affect the peak make limitation (although only for
relatively small values of R0), but Ic (and τ) can be selected in line with empirical results of
superconductor quenching to approximate the behaviour of a particular SFCL device. The
superconductor recovery time is not modelled in this study but it is assumed that the SFCL must be
removed from service during the post-fault period, as discussed in Section 4.4. A typical SFCL
resistance characteristic is shown in Figure 4.
Figure 4: Typical per phase SFCL resistance characteristic and effect on fault current
2.3 Fault level analysis
Table 1 lists the magnitudes of currents evident at three different fault locations, with the bus-tie
circuit breaker closed and with no fault current limitation. For each location the peak make, peak
break (equivalent to the peak magnitude at the third cycle after fault inception – chosen to be
reflective of the time at which the breaker may trip after delays associated with protection relay and
breaker operation times), and RMS break (RMS value of current at the fifth peak, an approximation of
the RMS steady-state symmetrical fault component ) values are provided. Fault F3 is not shown
because it results in very similar fault currents to those associated with fault F1; however different
results are obtained depending on the SFCL location(s), as shown in Sections 3 and 4. For fault F4,
Table 1 implies that the DC offset decays very slowly, after approximately several seconds, due to the
increased X/R ratio caused by the transformer impedance in the fault current path. However, the
potential for damage due to short circuits on the 230V distribution system are by comparison
significantly lower – due to the additional transformer impedance in the current path – and are
therefore not considered further in this paper. The generator feeder fault current (fault F2) is less than
the bus-tie fault current (fault F1) due to the cable impedance between the locations, which reduces
the fault contribution from the four 2.1MW generators.
690V bus (fault F1)
Generator feeder (fault F2)
230V bus (fault F4)
Peak make (kA)
Peak break (kA)
RMS break (kA)
Table 1: Prospective fault currents (without fault current limitation)
Figure 5 illustrates the total unrestricted fault current for fault F1, where the fault occurs after 1
second and is present for 0.1 seconds. For an electrical system with 16.4MW of generation capacity, a
fault current approaching 250kA peak is calculated, which may be prohibitively high. Fault F1 occurs
at a voltage zero-crossing on phase A; hence phase A exhibits the highest possible peak fault current
due to the increased DC component associated with the point-on-wave of fault inception . Other
point-on-wave fault inceptions, where the fault does not occur at a voltage zero-crossing on any of the
phases, result in a lower peak fault current, close to the peak symmetrical short-circuit calculation 
Figure 5: Fault F1 on the 690V bus (without SFCL)
2.4 Voltage and power perturbations
Figure 6 presents the bus voltages for fault F1 at t=1s, calculated as the sum of the squares of the
instantaneous voltage in each phase, scaled to a per unit value as expressed by Equation (2). This
approach is used because the averaging caused by an RMS measurement may obscure transients. The
dip in voltage is clearly apparent in Figure 6 and it is evident that the voltage starts recovering soon
after faults are cleared. For the same fault conditions, Figure 7 illustrates the disturbance to real and
reactive power at the output of the 4MW generator in the right subsystem. Clearly, the nature of the
prime movers, generators and their control systems will influence post-fault behaviour.
3? 2 ??(?)2+ ??(?)2+ ??(?)2
Equation 2: Calculation of instantaneous per unit voltage
Figure 6: Bus voltages for fault F1 at t=1s (without SFCL)
Figure 7: P and Q at the right subsystem 4MW generator for fault F1 at t=1s (without SFCL)
It is clear from the analysis presented in this section that fault currents in marine systems may be
excessively high, that voltages throughout the system will be seriously depressed and that the ability
to provide power to un-faulted parts of the systems will be severely limited during faults and for a
short period following fault clearance while the overall system returns to a state of equilibrium. This
could lead to the possibility of system-wide disturbances or even blackouts for a single fault anywhere
in the system.
3 The impact of SFCLs on fault currents for different SFCL locations and resistance
3.1 Overview of SFCL location strategies and their impact on fault currents
Initially, each SFCL location strategy has been tested with an SFCL impedance of 0.2Ω, and a fault at
the 690V bus-tie (fault F1). Table 2 compares the results and Figure 8 illustrates the total fault current
for location strategy A, which is approximately halved in magnitude compared to the unrestricted case
shown in Figure 5.
Peak make (kA)
Peak break (kA)
RMS break (kA)
Table 2: Comparison of impact of SFCL location on fault currents
Figure 8: Fault current limitation for fault F1 at location A
By inspection of the system topology, location A is an attractive option because it has the potential to
limit the fault current contribution from one half of system, regardless of the fault location. Table 2
confirms that peak make, peak break, and RMS break are all approximately halved, even for a
relatively small SFCL resistance value. The main disadvantage of this approach is that a single SFCL
device is required to be rated to handle the current caused by the fault, and hence the energy
dissipated in the SFCL.
Location strategy B clearly limits the fault current contribution from all generators (except for faults
across a generator's terminals), reducing the fault current to less than 30% of its prospective value.
However, this is unlikely to be used in practice because the SFCLs may require post-fault recovery
, necessitating all generation (except the emergency generator) to be removed from service. In
addition, six separate fault current limiters are required, albeit of smaller current rating.
Strategy C is a compromise of the advantages and disadvantages of strategy B, and restricts the
contribution only from the 4MW generators. The result in Table 2 for peak make for this SFCL
location is relatively high, because of the relatively large peak make contribution from the 2.1MW
generators (due to their relatively small sub-transient reactance; see Appendix).
Table 2 illustrates that location D offers better fault current limitation than location A. It also has the
advantage that it can limit fault currents for all fault locations when the main bus-tie circuit breaker is
open. Hence, the impact of SFCLs located at D will be analysed in more detail in Section 3.2, and this
location is compared to location A in terms of other effects on the electrical system in Section 4.
3.2 Effects of different SFCL resistance and fault location
Figure 9 and Figure 10 illustrate respectively how SFCL resistance affects the peak make and RMS
break fault currents. It can be observed that in most cases there is only a small reduction in fault
current for resistance values greater than approximately 0.2Ω, as the equivalent impedance of the
loads in the system, which effectively remain ”in circuit” when the SFCL develops full resistance, are
significantly lower than this value (e.g. for a system load of approximately 8MW, the impedance is
0.02Ω). For location B and with an SFCL resistance of greater than approximately 0.25Ω, the peak
fault current contribution from each generator is typically less than twice load current, and diminishes
to load current levels or less after the first peak. Such severe fault current limitation could potentially
lead to use of smaller, lighter, and less expensive switchgear. Note that the slight increase in the total
fault current, for example with location C at 0.5Ω in Figure 9, is due to the fault current being limited
sufficiently (below Ic) such that one phase of the SFCL does not quench. This implies that a two-
phase SFCL may sufficiently reduce fault currents in unearthed electrical systems (noting that the
voltage in the limited phases will rise by a factor of 3 of the nominal value), leading to potential
savings in size, weight and cost . Furthermore, only a certain range of SFCL resistance values will
cause a two-phase quench in a three-phase SFCL; this will not be discussed further in this paper but
will be investigated and reported on in the future.
Figure 9: Peak make fault current for fault F1, for alternative SFCL locations
Figure 10: RMS break fault current for fault F1, for alternative SFCL locations
By inspection, location D has the potential to limit approximately half of the steady-state fault current
for faults at the bus-tie. Figure 10 shows that an SFCL resistance of approximately 0.2Ω is necessary
to achieve this. In the case study system, a resistance of 0.2Ω also reduces the peak fault current by
more than half of the unrestricted value due to the relatively small sub-transient reactance of the
2.1MW generators. However, this SFCL deployment strategy does not limit the fault contribution
from either of the two 4MW generators, for faults at the bus-tie or one of the 4MW generator feeders
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(fault F1 or F2). In the latter case, relatively large values of SFCL resistance only trim approximately
one third off the fault current, as shown in Table 3. However, Table 4 illustrates that location D is
highly effective at limiting faults elsewhere on the 690V bus, at location F3.
Peak make (kA)
Peak break (kA)
RMS break (kA)
Table 3: Comparison of limitation for SFCL location D, for fault F2
Peak make (kA)
Peak break (kA)
RMS break (kA)
Table 4: Comparison of limitation for SFCL location D, for fault F3
4 Other SFCL application considerations
This section introduces several issues – other than the level of fault current limitation – that will be
pertinent when considering the role of SFCLs in a marine application. The previous section identified
that locations A and D are effective at limiting fault currents; hence they are explored in more detail
in this section. Faults F1 and F3 are examined in each case.
4.1 Effects of SFCL on system voltage, power and frequency
The simulation in Section 2.4 has been extended to examine the effects that SFCLs have on system
voltage, power and frequency, and to help assess the nature of system recovery following a fault and
whether this recovery process may be assisted by SFCLs. In each case, a fault is applied at t=1s and
the bus-tie circuit breaker is opened after approximately 100ms (depending on the individual phase
current zero-crossings). This clears the fault from the right subsystem. The left subsystem must open