Article

Proteus: An ASIC Flow for GHz Asynchronous Designs

Univ. of Southern California, Los Angeles, CA, USA
IEEE Design and Test of Computers (Impact Factor: 1.62). 11/2011; DOI: 10.1109/MDT.2011.114
Source: IEEE Xplore

ABSTRACT Editors' note:The high-performance benefits of asynchronous design have hitherto been obtained only using full-custom design. This article presents an industrial-strength asynchronous ASIC CAD flow that enables the automatic synthesis and physical design of high-level specifications into GHz silicon, greatly reducing design time and enabling far wider use of asynchronous technology.

0 Bookmarks
 · 
173 Views
  • [Show abstract] [Hide abstract]
    ABSTRACT: As multi-core systems transition to the many-core realm, the pressure on the interconnection network is substantially elevated. The Network-on-Chip (NoC) is expected to undertake the expanding demands of the ever-increasing numbers of processing elements, while—at the same time—technological and application constraints increase the pressure for increased performance and efficiency with limited resources. Although NoC research has evolved significantly the last decade, essential questions remain un-answered and call for fresh research ideas and innovative solutions. In this paper, we summarize a selected set of NoC-related research challenges, with the hope to guide future development and trigger high-impact research progress.
    Design Automation for Embedded Systems 01/2014; · 0.24 Impact Factor
  • [Show abstract] [Hide abstract]
    ABSTRACT: This paper introduces reconditioning: a novel systematic technique for reducing unnecessary switching activity of asynchronous gate-level net lists, which involves the optimal reordering of conditional communication and logic primitives. Our technique is applicable to asynchronous circuits with handshaking protocols that encode data and control together, in particular, QDI and 1-of-N handshaking circuits. Both an optimal integer linear program (ILP) and a fast heuristic algorithm are presented. We show that our ILP is feasible for moderate size circuits and our heuristic algorithm scales to much larger circuits, completing in seconds on circuits with tens of thousands of gates. Our experimental results shows power improvement highly depends on the structure of the circuit but can often be above 40% with typically less than 5% area overhead.
    2014 20th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC); 05/2014
  • [Show abstract] [Hide abstract]
    ABSTRACT: Asynchronous techniques are regaining relevance in the VLSI research community as they allow increasing robustness against process variability considerably, by relaxing timing assumptions. In addition, asynchronous circuits enable achieving low-power and high-speed designs. However, due to the absence of commercial dedicated standard cell libraries to take the most of asynchronous design, such circuits implementations are relegated to full-custom approaches only. This limits applicability of asynchronous solutions and avoids further development of dedicated design automation tools. This paper describes an improvement to this situation by proposing a fully-automated design-flow called ASCEnD-A, able to implement standard cells specifically required for asynchronous circuits design. The flow is capable of generating cells at the layout level, providing physical, power and timing models required by cell-based flows available in the state-of-the-art technologies.
    27th Symposium on Integrated Circuits and Systems Design (SBCCI 2014), Aracaju; 09/2014

Preview (4 Sources)

Download
3 Downloads
Available from