Proteus: An ASIC flow for GHz asynchronous designs

Univ. of Southern California, Los Angeles, CA, USA
IEEE Design and Test of Computers (Impact Factor: 1.62). 11/2011; 28(5):36 - 51. DOI: 10.1109/MDT.2011.114
Source: DBLP

ABSTRACT Editors' note:The high-performance benefits of asynchronous design have hitherto been obtained only using full-custom design. This article presents an industrial-strength asynchronous ASIC CAD flow that enables the automatic synthesis and physical design of high-level specifications into GHz silicon, greatly reducing design time and enabling far wider use of asynchronous technology.

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    • "Other approaches use reachability analysis and model checking, including techniques to incorporate timing constraints, to validate implementations , such as are included in the Petrify tool [7], which can also formally check the consistency and well-formedness of specifications. Simulation, and functional and timing validation, techniques have also been developed for industrial flows at Tiempo [24] and Fulcrum/Intel [20]. "
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    ABSTRACT: This two-part article aims to provide both a short historical and technical overview of asynchronous design, as well as a snapshot of the state of the art. Part 1 covered foundations of asynchronous design, and highlighted recent applications, including commercial advances and use in emerging application areas. Part 2 focuses on methodologies for designing asynchronous systems, including basics of hazards, synthesis and optimization methods for both logic-level and high-level synthesis, and the development of specification languages and CAD tool flows. Finally, two sidebars provide a summary of asynchronous processors and architectures, as well as testing.
    IEEE Design and Test 06/2015; 32(3):1-1. DOI:10.1109/MDAT.2015.2413757 · 0.78 Impact Factor
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    • "Accordingly, transistors involved in feedback loops are always minimum size to interfere the least in the cell performance. However, we advise designers to use static versions of these schemes to avoid crosstalk and PVT varia­ tions problems [4]. "
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    ABSTRACT: Asynchronous techniques are regaining relevance in the VLSI research community as they allow increasing robustness against process variability considerably, by relaxing timing assumptions. In addition, asynchronous circuits enable achieving low-power and high-speed designs. However, due to the absence of commercial dedicated standard cell libraries to take the most of asynchronous design, such circuits implementations are relegated to full-custom approaches only. This limits applicability of asynchronous solutions and avoids further development of dedicated design automation tools. This paper describes an improvement to this situation by proposing a fully-automated design-flow called ASCEnD-A, able to implement standard cells specifically required for asynchronous circuits design. The flow is capable of generating cells at the layout level, providing physical, power and timing models required by cell-based flows available in the state-of-the-art technologies.
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    • "The class of Null Convention Logic (NCL) gates [17], [18] allows efficient implementation of 1-of-n 4-phase QDI circuits as demonstrated by the Theseus Logic company through the design and fabrication of several chips [12]. In fact, all revised works on QDI design automation rely on the usage of NCL gates (consider that C-elements are special cases of NCL gates), except for the approach presented in [7] that uses dynamic logic templates. Here the authors consider the use of NCL for QDI design and seek to answer to if and how " it is possible to employ commercial EDA frameworks to realize technology mapping and design optimization using NCL gates " . "
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    ABSTRACT: Quasi-Delay-Insensitive design is a promising solu-tion for coping with contemporary silicon technology problems such as aggressive process variation and tight power budgets. However, one major barrier to its wider adoption is the lack of support for automated optimization techniques in semi-custom design flows. This paper proposes an innovative design flow that relies on the use of consolidated commercial EDA frameworks for synthesizing 1-of-n 4-phase Quasi-Delay-Insensitive circuits using Null Convention Logic. Accordingly, asynchronous gates, which are usually not supported by these frameworks, are modelled as conventional logic gates, allowing synthesis tools to perform static timing analysis and pre-and post-mapped design optimizations that can be specified by the designer using conventional timing constraints.
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