Fast constant weight codeword to index converter

Abstract

Constant weight codewords, in which the number of 1's is constant, are essential to combinatorial computing. For example, it is often useful to generate all subsets of a set with a fixed number of elements. In this paper, we show an efficient circuit that converts a constant weight codeword into a unique index of that codeword. This circuit is a necessary part of a circuit that uses constant weight codewords to transmit data on and off chip. Our circuit is based on the combinatorial number system in which the digits are binomial coefficients (_rⁿ). Experimental results show the efficiency of our design.

Full text

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Fast Constant Weight Codeword to Index
Converter
J. T. ButlerT. Sasao
Department of Electrical and Computer Engineering
Naval Postgraduate School
Monterey, CA U.S.A.
Department of Computer Science and Electronics
Kyushu Institute of Technology
Iizuka, Fukuoka, JAPAN
Abstract—Constant weight codewords, in which the number
of 1’s is fixed, are essential to many coding applications. In this
paper, we show an efficient circuit that converts a constant weight
codeword into a unique index of that codeword. For example,
this circuit is necessary when constant weight codewords are
used to transmit data on and off chip. Our circuit is based on
the combinatorial number system in which the digits are binomial
coefficients. It has O(n3) area complexity and O(n) delay, where
n is the number of variables. Two types of circuits are proposed.
Various constant weight codes are implemented on an FPGA,
including a 64-out-of-128 code. These implementations support
our complexity analysis.
Keywords: constant weight codewords, converters, encoding
I. INTRODUCTION
A constant weight code to index converter is needed when
constant weight Gray codes are used to encode data in flash
memory. In local rank modulation [2], data stored in flash
memory is viewed as an n-bit constant weight codeword that
differs in exactly two bits from an adjacent memory location
(because of overlap). All codewords in this encoding have the
same weight (number of 1’s).
Balanced codes, with as many 0’s as 1’s, can be used to
transfer data on and off VLSI chips so that the current fluctu-
ations are minimized [7]. On the other hand, codes with small
weight are desired in this application because they yield faster
and more compact circuits [7]. Constant weight codewords
can be used to counter “side-channel” attacks against secure
systems [4]. Such attacks use data dependent differences in
power consumption to extract hidden information. Constant
weight codewords have been used in asynchronous logic to
implement delay-insensitive codewords [8].
The use of constant weight codewords requires two parts,
an index to constant weight code converter and a constant
weight code to index converter. We considered the first part
in [1]. However, we have not seen a hardware implementation
of the second part, except for an implementation that requires
O(2n) complexity [6]. In this paper, we propose an imple-
mentation with O(n3) complexity. In Section II, we discuss
the combinatorial number system. We show how it can be
used to convert a constant weight codeword to an index, and
we present its circuit implementation. Then, in Section III, we
show an improvement to this circuit that significantly reduces
delay for large n. Finally, in Section IV, we give concluding
remarks.
II. THE COMBINATORIAL NUMBER SYSTEM
A. Introduction
The basis for our constant weight code to index converter
is the combinatorial number system [3].
Definition 1. In an?n
where
r
?combinatorial number system [5],
an integer N <
?n
?
r
?
is represented as N = crcr−1...c1,
N =
?cr
r
+
?cr−1
r − 1
?
+ ... +
?c1
1
?
,
(1)
and cr> cr−1> ... > c1≥ 0.
Example 1. Table I shows the representation of integers in
the
3
combinatorial number system. The leftmost column
shows the integer’s value in decimal and its vector represen-
tation. The middle column shows how this value is computed
according to (1). The rightmost column of Table I shows the
corresponding 6 bit constant weight code. Note that the three
elements of the vector representation shown in the leftmost
column correspond to the positions of the 1’s in the constant
weight codeword. For example, 19 = 5 4 3 corresponds to
111000, there being 1’s in positions 5, 4, and 3.
?6
?
(End of Example)
B. Circuit Implementation
A major contribution of this paper is to show how the
combinatorial number system can be used to realize an ef-
ficient circuit that transforms a constant weight codeword to
the index for that codeword. Such a circuit has for inputs the
values of the rightmost column of Table I (the bits of the
constant weight code) and has as outputs the standard binary
number representation of the numbers shown in the leftmost
column (the values of the index N). As shown in Table I, the
1-bits in the constant weight code contribute a value to its
corresponding index depending on the 1 bit’s position in the
codeword. For example, from Table I, the 1’s in the codeword
111000 contribute
32
can be seen in Fig. 1, which shows a circuit that converts a
3-out-of-6 constant weight codeword into the corresponding
index of that codeword.
?5
?,
?4
?, and
?3
1
?, from left to right. This

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Fast Constant Weight Codeword to Index Converter
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14. ABSTRACT
Constant weight codewords, in which the number of 1?s is fixed, are essential to many coding applications.
In this paper, we show an efficient circuit that converts a constant weight codeword into a unique index of
that codeword. For example this circuit is necessary when constant weight codewords are used to transmit
data on and off chip. Our circuit is based on the combinatorial number system in which the digits are
binomial coefficients. It has O(n3) area complexity and O(n) delay, where n is the number of variables.
Two types of circuits are proposed. Various constant weight codes are implemented on an FPGA including
a 64-out-of-128 code. These implementations support our complexity analysis.
15. SUBJECT TERMS
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TABLE I
THE?6
3
?COMBINATORIAL NUMBER SYSTEM FOR 0 ≤ N ≤ 19
N
Computing the Value of N
for r = 3
?5
3
2
1
?5
3
2
1
?5
3
21
?5
3
2
1
?5
3
2
1
?4
32
?4
32
?4
3
2
?3
3
2
?3
3
2
Const Wght Code
543210
19 = 5 4 3
18 = 5 4 2
17 = 5 4 1
16 = 5 4 0
15 = 5 3 2
14 = 5 3 1
13 = 5 3 0
12 = 5 2 1
11 = 5 2 0
10 = 5 1 0
9 = 4 3 2
8 = 4 3 1
7 = 4 3 0
6 = 4 2 1
5 = 4 2 0
4 = 4 1 0
3 = 3 2 1
2 = 3 2 0
1 = 3 1 0
0 = 2 1 0
3
?+?4
?+?4
?+?3
?+?3
?+?2
?+?3
?+?3
?+?2
?+?2
?+?1
2
?+?3
?+?1
?+?2
?+?0
?+?0
?+?2
?+?0
?+?0
?+?1
?+?0
1
?= 10 + 6 + 3
?= 10 + 6 + 1
?= 10 + 3 + 2
?= 10 + 3 + 0
?= 10 + 1 + 0
?= 4 + 3 + 2
1
?= 4 + 3 + 0
1
?= 4 + 1 + 0
1
?= 1 + 1 + 1
1
?= 1 + 0 + 0
1
111000
110100
110010
110001
101100
101010
101001
100110
100101
100011
011100
011010
011001
010110
010101
010011
001110
001101
001011
000111
?5
?5
?5
?5
?5
?4
?4
?4
?3
?2
?+?4
3
?+?4
3
?+?3
3
?+?2
3
?+?1
3
?+?3
3
?+?2
3
?+?1
3
?+?2
3
?+?1
?+?2
2
?+?0
2
?+?1
2
?+?1
2
?+?0
2
?+?1
2
?+?1
2
?+?0
2
?+?0
2
?+?0
?= 10 + 6 + 2
1
?= 10 + 6 + 0
1
?= 10 + 3 + 1
1
?= 10 + 1 + 1
1
?= 10 + 0 + 0
1
?= 4 + 3 + 1
1
?= 4 + 1 + 1
1
?= 4 + 0 + 0
1
?= 1 + 1 + 0
1
?= 0 + 0 + 0
Constant Weight


( )
0
1

Codeword
0
5
4
3
2
1
???
?
?
?
?
Index
?
Valid

( )
1
1

( )
5
3
( )
4
3
( )
2
3
( )
1
2
( )
2
2
( )
3
2
( )
4
2
( )
3
1
( )
2
1
( )
3
3
4 3 2
5
Fig. 1.Constant Weight Codeword to Index Converter Circuit.
( )
q
p
xi
Fig. 2.Decoder and Binomial Constant Generator.
This circuit contains an array of decoders that control which
digits occur in the combinatorial number. Fig. 2 shows the
detail of the decoders and the tri-state circuit that provides
constants for the combinatorial number. We can make the
following observations.
1) If a 1 occurs on either or both inputs to the OR gate in
the upper left hand corner of the decoder, then a 1 is
produced at exactly one of the two outputs. Specifically,
if xi, the input driving the decoder is 1, then a 1 appears
at the horizontal output (solid line), and a 0 appears at
the vertical output (dotted line). On the other hand, if xi
is 0, then a 0 appears at horizontal output and a 1 appears
at the vertical output. However, if both inputs to the OR
gate in the upper left hand corner are 0, then both the
horizontal and vertical outputs produce 0.
2) There is a path of 1’s through the array of decoders in
Fig. 1 beginning at the upper left hand corner. The path is
determined by the values of xiin the constant codeword.
For example, if x5x4x3x2x1x0= 111000, then the three
decoders along the top of the array of decoders starting
from the upper left hand decoder all produce 1 at their
horizontal outputs. This is because their inputs, x5, x4,
and x3, are 1. However, the decoder in the upper right
hand corner is driven by x2, which is 0. So, the 1 at
its OR gate input is directed now to its vertical output
(while its horizontal output is 0). Because x1and x0are
both 0, this 1 is directed downward (along dotted lines)
through two decoders into the 2-input OR gate that drives
Valid. That is, when x5x4x3x2x1x0= 111000, Valid
is 1, indicating the input codeword is a valid 3-out-of-6
codeword.
3) All other valid codewords result in a path of 1’s from the
upper left hand corner to the lower right hand corner,
causing Valid to be 1. Conversely, a non-codeword
causes Valid to be 0.
4) All horizontal lines from decoders drive binomial co-
efficient generators which apply to one of three bus
lines that drive inputs of an adder whose output is the
Index. Specifically, a 1 on the horizontal line causes the

Page 4

corresponding binomial coefficient generator to drive its
line. A 0 disconnects the binomial coefficient generator.
For example, in the case of x5x4x3x2x1x0= 111000, the
three horizontal lines driven by decoders cause?5
in 19 at the output, which is the index of 111000.
5) As shown in Fig. 1, each input to the adder is driven by
four binomial coefficient generators. The first (leftmost) 1
in the constant weight codeword specifies which binomial
coefficient generator drives the left input of the adder. The
second 1 determines which drives the middle adder input,
and the third (rightmost) 1 determines which drives the
right adder input.
3
?,?4
2
?,
and?3
1
?to be applied to the three adder inputs resulting
C. Complexity of Implementation
The complexity of the constant weight code to index
converter, is dominated by the array of binomial coefficient
generators and decoders. This array is a rectangle of r +1 by
n−r+1 cells, for a total of (r+1)(n−r+1) cells. With r =n
the (worst case) number of cells is O(n2). The decoder has
a complexity that is independent of n. However, the binomial
coefficient generator requires O(n) tri-state buffers. That is,
the binomial coefficient with the most tri-state buffers is the
one in the upper left hand corner; it realizes
requires no more that O(n) tri-state buffers. Thus, the total
complexity is O(n3). And so, the constant weight codeword
to index converter has complexity polynomial in n. Table
II shows the exact number of tri-state buffers and decoders
needed in the proposed constant weight codeword to index
converter. In the case of the tri-state buffers, the array cell at
the top of each column corresponds to the largest binomial
coefficient in that column and thus determines the number of
bits needed for that adder input.
2,
?n−1
r
?, which
TABLE II
THE NUMBER OF TRI-STATE BUFFERS AND DECODERS NEEDED IN THE
CONSTANT WEIGHT CODEWORD TO INDEX CONVERTER
nr
# of
tri-state decoders
# of
4
6
8
10
12
14
16
18
20 10
22 11
24 12
2
3
4
5
6
7
8
9
12
36
90
9
16
25
36
49
64
81
100
121
144
169
162
266
424
648
920
1254
1680
2184
The longest path in the circuit is from xn−1 through the
array to the Valid output, and it is O(n). The delay of the
adder can be neglected, since it is O(logn). Thus, the overall
delay is O(n).
D. FPGA Resources Used
To understand how the complexity of a?n
pends on n and r, we implemented this system for various n
and r on the 40 nm Altera Stratix IV EP4SE530F43C3NES
FPGA. Table III shows the delay obtained and the resources
used in this implementation. The leftmost column shows the
constant weight code as a binomial number. For example,
?128
to represent the largest this code. The third column gives
the delay achieved, which is inversely proportional to the
frequency of the circuit. The rightmost column gives the
number of ALMs needed to realize this circuit, which a
measure of the area. Although this table shows only balanced
constant weight code generators where the number of bits is
a power of 2, our approach applies to any number of bits and
to any weight.
r
?
combinatorial
number system constant weight code to index converter de-
64
?
corresponds to a 64-out-of-128 bit code. The second
column shows how many bits in the output Index are needed
TABLE III
DELAY AND RESOURCES USED TO REALIZE COMBINATORIAL NUMBER
SYSTEM CONSTANT WEIGHT CODE GENERATORS ON THE ALTERA
STRATIX IV EP4SE530F43C3NES FPGA.
Con. Wgt.
Code?n
2
?8
8
?32
32
?128
# Bits
Index
Freq.
(MHz
Delay
(ns.)
Est. # of
Packed ALMs
r
?
?4
?16
16
?64
64
?
?
?
3
7
261.6
178.7
104.4
57.5
31.5
15.2
3.8
5.6
9.6
17.4
31.7
65.8
2 (0%)
17 (0%)
120 (0%)
647 (0%)
3,203 (1%)
20,497 (9%)
4
?
?
14
30
61
?
125
Our circuit was synthesized using Synplify Pro and modeled
using ModelSim. A large codeword is achievable; a 64-out-
of-128 bit converter uses only 9% of the available ALMs. The
large values of n required special Verilog programming. For
example, to implement the 64-out-of-128 bit constant weight
codeword to index converter requires that the binary value
of
64
be applied to the adder circuit. This value is much
too large for Synplify Pro. To overcome this deficiency, we
computed the binary value of
in a MATLAB program and wrote it to a header file that was
included in the Verilog code.
?127
?
?127
64
?
and other values of
?n
r
?
III. COMPLEX DISJOINT DECOMPOSITION SOLUTION
It can be see from Fig. 1 that the longest path through the
array of the constant weight codeword converter has length
n, where n is the number of bits in the constant weight
code. In computing the index, each 1 contributes a value that
depends on the number of 1’s that preceded it. A 1 in the
leftmost bit position is an exception to this. This 1 always
contributes?6
a combinatorial number in which the most significant digit is
?5
3
?= 10. This can be seen in Table I; the constant
?. However, a 1 in the second bit from the left contributes
weight codewords with a 1 in the leftmost bit corresponds to
3

Page 5

a different value to its combinatorial number representation
depending on whether the leftmost bit is 1 or 0. If 1, then the
second 1 contributes?4
the least significant bit, whether 0 or 1 contributes 0 to the
combinatorial number’s value. This is because that bit is
”forced” to be 0 or 1 depending on whether there are six
or five 1 bits to its left. However, note that the right digit of
the combinatorial number’s value is 1 iff the least significant
bit of the constant weight code is 0. This can also be seen
in the circuit of Fig. 1. Here, if x0 is 1, then 0 drives the
least significant digit, and none of the other three binomial
coefficients can drive this least significant digit. That is, x0
and the only decoder it drives is the ”mirror” image of x5and
the only decoder it drives. Similarly, x1and the two decoder
it drives are the mirror image of x4 and the two decoder it
drives. Therefore, we can realize the same circuit by reversing
the decoders in Fig. 1 that are driven by x2, x1, and x0. The
new circuit is shown in Fig. 3.
Constant Weight
5
2
?. If 0, then it contributes?4
3
?.
A similar phenomena exists at the right side. Interestingly,

( )
5
3
( )
4
3
( )
2
3
( )
1
2
( )
2
2
( )
3
2
( )
4
2
( )
2
1
( )
1
1
( )
0
1
( )
3
3
Codeword
2
4
3
1
0
???
?
?
?
?
Index
Valid
?
?
??
?
( )
3
1
4 3 2
5
Fig. 3.
Two Subcircuits.
In the new circuit, the inputs are divided into two parts
{x5,x4,x3} and {x2,x3,x1}, where each part drives a sepa-
rate subcircuit. The two subcircuits, in turn, drive inputs to the
adder, which, in turn, drives the Index output. Such a circuit
is said to have a complex disjoint decomposition (CDD).
Table IV shows the delay achieved and the resources used
for the CDD circuit. The benefit of the new circuit is its
reduced delay, especially in large circuits. This can be seen
by comparing Tables IV and III. For example, for 64-out-of-
128 codes, the delay of circuit consisting of two subcircuits is
Constant Weight Codeword to Index Converter Circuit Consisting of
TABLE IV
DELAY AND RESOURCES USED FOR THE CDD CONSTANT WEIGHT
CODEWORD TO INDEX CONVERTER ON THE ALTERA STRATIX IV
EP4SE530F43C3NES FPGA.
Con. Wgt.
Code?n
2
?8
8
?32
32
?128
# Bits
Index
Freq.
(MHz)
Delay
(ns.)
Est. # of
Packed ALMs
r
?
?4
?16
16
?64
64
?
3
7
262.9
193.5
127.9
80.8
47.8
23.6
3.8
5.2
7.8
12.4
20.9
42.4
3 (0%)
16 (0%)
116 (0%)
657 (0%)
3,503 (1%)
20,723 (9%)
4
?
?
?
14
30
61
125
?
?
64% that of the full rectangle circuit.
IV. CONCLUDING REMARKS
Although there is a need for a circuit that computes an index
from a constant weight codeword, we have not seen a simple
implementation. We show a circuit based on the combinatorial
number system that has complexity O(n3), where n is the
number of bits in the code. Our circuit is useful, for example,
in the encoding/decoding of data, such as between on-chip
and off-chip and in delay-insensitive logic for asynchronous
circuits. It has only O(n) delay. We also show an improvement
that reduces by about half the delay that still has O(n3)
complexity. We have implemented our designs on an Altera
Stratix IV EP4SE530F43C3NES FPGA. This has shown that
both circuits are efficiently implemented.
V. ACKNOWLEDGMENTS
This research is supported by a Knowledge Cluster Initiative
(the second stage) of MEXT (Ministry of Education, Culture,
Sports, Science and Technology).
REFERENCES
[1] J. T. Butler and T. Sasao, ”High-speed constant weight code generators,”
7th Inter. Symp. on Applied Reconfigurable Computing (ARC2011),
Proceedings Lecture Notes in Computer Science (LNCS 6576), Springer-
Verlag Berlin Heidelberg, 2011, A. Koch et al (eds.), Belfast, N. Ireland,
Mar. 23-25, 2011, pp. 193-204.
[2] E. Gad, M. Langberg, M. Schwartz, and J. Bruck, “Constant-weight Gray
codes for local rank modulation,” Proc. of the 2010 IEEE International
Symposium on Information Theory, ISIT2010, pp. 869-873, Austin, TX,
U.S.A., June 2010.
[3] Combinadic - http://en.wikipedia.org/wiki/Combinadic.
[4] http://en.wikipedia.org/wiki/Side_channel_attack.
[5] D. E. Knuth, The Art of Computer Programming, “Generating all com-
binations and partitions,” Vol. 4, Fascicle 3, Addison-Wesley, pp. 5-6,
ISBN 0-321-58050-8, (2009).
[6] T. Sasao, Memory Based Logic Synthesis, 1st Edition, Springer, ISBN
978-1-4419-8103-5, (2011)
[7] L. G.Tallini and B. Bose, “Design of balanced and constant weight
codes for VLSI systems,” IEEE Trans. on Computers, Vol. 47, No. 5, pp.
556–572, (1998)
[8] T. Verhoeff, “Delay-insensitive codes - an overview,” Distr. Comp, 3(1):1-
8, (1988)