Analysis and Design of Nanoscale CMOS Storage Elements for Single-Event Hardening With Multiple-Node Upset

Abstract

The occurrence of a single event with a multiple-node upset is likely to increase significantly in nanoscale CMOS due to reduced device size and power supply voltage scaling. This paper presents a comprehensive treatment (model, analysis, and design) for hardening storage elements (memories and latches) against a soft error resulting in a multiple-node upset at 32-nm feature size in CMOS. A novel 13T memory cell configuration is proposed, analyzed, and simulated to show a better tolerance to the likely multiple-node upset. The proposed hardened memory cell utilizes a Schmitt trigger (ST) design. As evidenced in past technical literature and used in this work, simulation of all node pairs by current sources results in an assessment similar to 3-D device tools; the simulation results show that the proposed 13T improves substantially over DICE in the likely and realistic scenarios of very diffused or limited charge sharing/collection. Moreover, the 13T cell achieves a 33% reduction in write delay and only a 5% (9%) increase in power consumption (layout area) compared to the DICE cell (consisting of 12 transistors). The analysis is also extended to hardened latches; it is shown that the latch with the highest critical charge has also the best tolerance to a multiple-node upset. Among the hardened latches, the ST designs have the best tolerance, and in particular, the transmission gate configuration is shown to be the most effective. Simulation results are provided using the predictive technology file for 32-nm feature size in CMOS. Monte Carlo simulation confirms the excellent multiple-node upset tolerance of the proposed hardened storage elements in the presence of process, voltage, and temperature variations in their designs.

Full text

Page 1

> REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) <

1
Analysis and Design of Nanoscale CMOS
Storage Elements for Single Event Hardening
with Multiple Node Upset
Sheng Lin, Student Member, IEEE, Yong-Bin Kim, Senior Member, IEEE, and Fabrizio Lombardi,
Fellow, IEEE

Abstract—The occurrence of a single event with a multiple node
upset is likely to increase significantly in nanoscale CMOS due to
reduced device size and power supply voltage scaling. This
current work presents a comprehensive treatment (model,
analysis and design) for hardening storage elements (memories
and latches) against a soft error resulting in a multiple node upset
at 32nm feature size in CMOS. A novel 13T memory cell
configuration is proposed, analyzed, and simulated to show a
better tolerance to the likely multiple node upset. The proposed
hardened memory cell utilizes a Schmitt trigger design. As
evidenced in past technical literature and used in this current
work, simulation of all node pairs by current sources results in an
assessment similar to 3D device tools; the simulation results shows
that the proposed 13T improves substantially over DICE in the
likely and realistic scenarios of very diffused or limited charge
sharing/collection. Moreover, the 13T cell achieves a 33%
reduction in write delay and only a 5% (9%) increase in power
consumption (layout area) compared to the DICE cell (consisting
of 12 transistors). The analysis is also extended to hardened
latches; it is shown that the latch with the highest critical charge
has also the best tolerance to a multiple node upset. Among the
hardened latches, the Schmitt trigger designs have the best
tolerance and in particular, the transmission gate configuration is
shown to be the most effective. Simulation results are provided
using the predictive technology file for 32nm feature size in
CMOS. Monte Carlo simulation confirms the excellent multiple
node upset tolerance of the proposed hardened storage elements
in the presence of process, voltage, and temperature variations in
their designs.

Index Terms—Memory Design, Nanotechnology, Radiation
Hardening, Soft Error.


Figure 1. DICE cell proposed in [6]
I. INTRODUCTION
S CMOS is moving into nanometric feature sizes, novel
circuits have been proposed. The operation of these
circuits exploits the high device density while meeting other
performance metrics (such as power consumption and delay).

Manuscript received February 9, 2011; revised June 25, 2011.
The authors are with the Department of Electrical and Computer
Engineering, Northeastern University, Boston, MA 02115 USA (e-mail: ybk,
lombardi, slin@ ece.neu.edu).
Copyright © 2011 IEEE. Personal use of this material is
permitted. However, permission to use this material for any other purposes
must be obtained by sending a request to pubs-permissions@ieee.org.

Scaling of CMOS has been made possible by improved
fabrication/manufacturing as well as design techniques;
however the reliable operation at nanometric feature sizes is of
significant concern. The amount of charge stored on a circuit
node is becoming increasingly smaller due to the lower supply
voltage and the smaller node capacitance. This makes circuits
more susceptible to spurious voltage and charge variations
caused by externally induced phenomena, such as cosmic ray
neutrons and α-particles [1]. These energy particles travel
through the silicon bulk and create minority carriers that may
be collected by the source/drain diffusion. They alter voltage
values [2] and data integrity could be changed [3] if storage
cells, such as memories and latches are affected by the
occurrence of this type of event. This event may result in a
transient fault (TF); if a TF is latched by a sampling element
(latch), then this may result in a so-called soft error (SE) [4].
The soft error rate (SER) is defined as the rate at which a device
(circuit or system) encounters SEs on a predictive basis. SER is
expected to be significantly higher for CMOS in the deep
submicron/nano ranges [5].
Many approaches have been proposed to deal with TFs in
storage elements, such as error correcting codes, temporal
redundancy, and hardened circuit design. Among them,
hardening has been utilized for low-cost design to tolerate
single SE and TF in memories and latches [6] - [9]. An example
of an hardening design approach has been reported in [6] and is
commonly known as DICE. The DICE cell is shown in Fig.1
A

Page 2

> REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) <

2
and uses twice the number of transistors of a standard storage
cell (i.e. 12T vs. 6T) to achieve tolerance against a TF affecting
any single node. The advantage of this design is that it does not
require an increase in the size of the transistors or the
capacitance of some nodes. In the DICE cell, the single node
that is affected by a TF can be driven back to its previous state
by the other transistors. A different hardened memory cell
requiring 11 transistors (i.e.11T) has been proposed in [10]; the
single node affected by a TF can be driven back by using novel
access and refreshing circuits. Theoretically, these two cells are
immune to any amount of charge collected at any single node.
However, as device size shrinks, spacing between nodes
decreases significantly and the charge generated from a single
event strike may diffuse to affect adjacent nodes. As circuits
are scaled down in size, the multiple node upset scenario is
likely to require new designs for hardening storage cells.
Therefore, differently from the reference work [11] in which
the multiple-bit upset tolerance is considered, the objective of
this study is to investigate the multiple node upset tolerance of
existing hardening (single-bit) cells (memories and latches) and
propose new hardening designs with better multiple node upset
tolerance. Charge sharing/collection is considered in the
multiple node upset modeling; using [12] – [14] simulation of
all node pairs (as attaining similar results to 3D device tools)
shows that the proposed design outperforms DICE in the
realistic scenarios of (diffused and limited) charge
sharing/collection among two adjacent nodes.
This technical paper is organized as follows. Section II deals
with modeling soft errors in nanometric circuits. Multiple node
upset modeling and tolerance of existing hardened memory
designs are analyzed in Section III. This multiple node upset
modeling technique is presented in [12] and its correctness has
been verified by 3D device simulation tools. A new 13T design
of the hardened memory cell is presented in Section IV and it is
shown to have a better tolerance to a multiple node upset.
Relevant figures of merit such as delay, layout and power are
analyzed and assessed in Section V. Section V also presents a
simulation-based assessment of variations and their effects on
the proposed 13T SRAM cell. Section VI details different
Schmitt trigger based designs of a latch for the multiple node
upset scenario and evaluates them by HSPICE versus existing
(single-node hardened) latch designs. Finally, Section VII
concludes this study.
II. SOFT ERROR MODELING
A soft error is said to occur when the collected energy Q at a
particular node is greater than the critical charge, Qcrit, i.e. Qcrit
is the minimum charge that needs to be deposited at the
sensitive node of a storage cell to flip (change) the stored bit
(data). In the model of [15], the SER is given by:
crit
s
Q
Q
flux
SERNCSe


. (1)
where Nflux is the intensity of the neutron flux, CS is the area of
the cross section of the node, and Qs is the charge collection
efficiency that strongly depends on doping. Qcrit is proportional
to the node capacitance and the supply voltage. In (1), Qcrit
exhibits an exponential relationship with the soft error rate;
therefore, Qcrit has been widely used as a metric for assessing
soft error occurrence. The charge at a single node (due to
cosmic ray neutrons or α-particle hits) generates a large
transient current at that node; therefore, a critical charge
generated on such node can be modeled as a current pulse for
HSPICE simulation.
Fig. 2 shows the soft error model of [16]. This model is also
used in this current work for HSPICE simulation. In this figure,
with no loss of generality and correctness, soft errors resulting
in a signal glitch occur at the inverter. Fig.2 (a) shows the case
in which the normal output value for the inverter is high and a
soft error occurring at the NMOS transistor generates a
negative pulse, whereas Fig.2 (b) shows the case in which the
normal output value for the inverter is low and soft error
occurring at the PMOS transistor generate a positive pulse.
The soft error on the critical node is modeled as a current
source injected to that node. For multiple node injection,
multiple current sources are applied to the circuit nodes. A
multiple node upset occurs when in the presence of a single
event more than one node are affected in the storage element
and additional charge is collected by those nodes. It is also
important to note that only the scenario of any two-node upset
is modeled in this current work. In the occurrence of a single
event, a multiple node upset scenario with more than two nodes
is unlikely to cause a significant state change due to the
extensive charge diffusion occurring in the storage element and
wider spread of the incident strike [11]. Therefore, the node
that collects the primary portion of the charge is referred to as
the primary node, while the node that collects the remaining
portion of the charge is referred to as the secondary node. To
simulate the charge collection on two adjacent nodes, the
charge is deposited simultaneously on node pairs using
multiple current sources [12]; this simulation-based approach
has been verified to yield the same correct results as a 3D
device modeling approach [12].
(a) (b)
Figure 2. Equivalent circuits used for simulation of (a) negative and (b)
positive glitches
III. EXISTING HARDENED MEMORY DESIGNS
In this section, the single node hardened capabilities of two
existing memory cell designs (i.e. DICE and 11T) are evaluated
with respect to a multiple node upset scenario. The charges on

Page 3

> REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) <

3

Figure 3. 11T hardened memory cell
the primary and secondary nodes are found to assess by
HSPICE simulation the tolerance of these designs to this new
scenario.
A. DICE Cell
As shown in Fig.1, the DICE cell uses twice the number of
transistors of a standard storage cell. The DICE cell has two
states, the 0 state (X1=0, X2=1, X3=0, X4=1) and the 1 state
(X1=1, X2=0, X3=1, X4=0). In any of these two states upon the
occurrence of a soft error (on a single node), the state of the
node is always driven back to its original value. For example, in
the 0 state, if the node struck by a particle is X2, the state of X2
goes from 1 to 0. However, this strike will not propagate along
the feedback loop due to the interlocked configuration.
Meanwhile, the state 0 stored in X1 can restore the state of X2;
however, when a single event (strike) occurs on multiple nodes,
the DICE cell is unable to drive back the original state. For
example, in the 0 state, if the node struck by a particle is X2, the
state of X2 goes from 1 to 0. Meanwhile, if node X1 is also
affected by the strike, then it goes from 0 to 1. In this case, due
to the strike on X1, the state of X2 will not be restored and a
soft error is said to occur. Simulation results show that if there
is a strike on X1, a very small amount of charge on X2 can
change the state of the DICE cell.
B. 11T Hardened Cell
A single node hardened memory cell has been proposed in
[10] and shown in Fig.3. The basic storage element used in this
memory cell relies on the hardening scheme of [8]. In the
memory cell of Fig.3, its feedback loop is cut off by the
transistors M5, M6, M7, and M8, i.e. for a single node upset, a
transient pulse cannot be propagated along this loop back to its
starting point. The gates of the PMOS and NMOS transistors
are separated from the hardened nodes a1 and a2. Signal
regeneration at a1 and a2 is controlled by the transistors M5 and
M8. In this cell, the access pass gates (M1 and M2) are
connected to node d instead of nodes a1 and a2 to prevent the
high leakage current from BL to change the data stored in the
memory cell. A TF on a1 or a2 will not change the data stored
in the memory cell. A NMOS write control transistor is added
to this memory cell for the write operation. As discussed in [17],
a single ended SRAM cell operates correctly when writing a
“0” as data, but it may encounter problems when writing a “1”.
Therefore, a write control transistor is added between M11 and
ground to write a “1” [17]. With this write control transistor, the
hardened memory cell consists of eleven transistors, i.e. one
transistor less than the DICE cell configuration. The 11T
memory cell is unable to restore the state of the node when a
single event causes a multiple node upset. Similar to the DICE
cell, the 11T cell has two states, the 0 state (d=0, db=1, a1=1,
a2=1) and the 1 state (d=1, db=0, a1=0, a2=0). If nodes a2 and
d are affected by a strike, the state of the 11T memory cell will
be changed, i.e. it has limited tolerance under a single event
with a two node upset.
C. Multiple Node Upset Modeling
In the past a multiple node upset has been evaluated using 3D
device simulation and a single current source [12]. Recently, it
has been shown that two independent current sources in
HSPICE can correctly model a multiple node upset using
circuit level simulation. To investigate the tolerance to the
single event scenario with a multiple node upset outlined
previously, two independent current sources are applied to the
cell nodes to find the most vulnerable node pairs for a storage
element such as a memory cell or a latch. In this current work,
this is referred to as the critical pair; the critical pair defines
two types of information: (a) the nodes that are affected by the
soft error and its transient fault; (b) the original and final states
of the nodes. In theory for a memory cell with N nodes, there
are at most 2N(N-1) combinations; in practice the number of
combinations is much less as dependent on the cell
functionality and circuit structure. For example, a conventional
6T cell has two internal nodes that may be affected by a particle
strike, hence there are four combinations. For the DICE cell,
there are 24 combinations, but only transient faults on adjacent
nodes will cause a multiple node upset (due to its feedback
feature). So, the number of combinations for the DICE cell is
reduced to 16. For the 11T memory cell of in Fig.3, particles
striking the NMOS transistor produce only negative current
pulses and particles striking a PMOS transistor produce only
positive current pulses. So, a particle striking node a2 can turn
transistor M11 off, but it can never turn it on, i.e. node a2 can
only go from state 1 to 0, but never from 0 to 1. Similarly, a
particle striking node a1 can turn transistor M10 off, but it can
never turn it on. Therefore, the number of combinations of the
11T cell is 12.
The process for finding the critical pair of a hardened storage
element starts from the critical node (as the node with the
lowest critical charge). This node is therefore identified as the
primary node. All node combinations with the primary node are
then simulated and the critical node pair is found. However, for
the 11T and the DICE memory cells, they are fully immune to a
single node upset. In this case, simulation of all possible
combinations must be performed to find the critical pair. The
exhaustive pair-wise node simulation of these memory cells has
been performed and the results show that the critical pair for the

Page 4

> REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) <

4
DICE cell is “x1 1->0 (i.e. the state of node x1 changes from 1
to 0), x4 0->1”, and the primary node for this pair is node x1.
Similarly, the critical pair for the 11T memory cell is “a2 1->0,
d 0->1”. Simulation results show that the 11T memory is more
vulnerable to a multiple node upset compared with DICE. To
improve its tolerance to a multiple node upset, two transistors
are added to the 11T memory cell, yielding a 13T memory
design, which will be described in more detail in the next
section.
Figure 5. Timing diagram of the proposed 13T memory cell

Figure 4. Proposed 13T hardened memory cell
IV. PROPOSED HARDENED MEMORY CELL
A new hardened memory cell is proposed in this current
work to improve the tolerance to a multiple node upset. Its
design is shown in Fig. 4. In the 11T memory cell, the critical
pair of the cell is “a2 1->0, d 0->1”, i.e. when node a2 stores a
state 1 and a charge is collected on the primary node a2, a
transient fault causes the node to change from state 1 to state 0.
At the same time under this scenario, charge is also collected by
the secondary node d; this causes the node to change from state
1 to state 0. Simulation results show that in order to improve the
tolerance to a multiple node upset, it is important to improve the
critical charge on the secondary node.
It is well known in electronic circuit design that a Schmitt
trigger affects the switching threshold of an inverter depending
on the direction of the input transition. The Schmitt trigger
configuration introduced in [18] is achieved with a feedback
mechanism to increase the switching threshold of the input
inverter [18]. Since the transition on node d is from 1 to 0, in the
proposed design the feedback mechanism is used only in the
pull-down path to improve the critical charge on the secondary
node, i.e. node d.
As shown in Fig.4, two additional transistors are added to the
11T memory cell, yielding a 13T design. The operation of the
13T memory cell is similar to the 11T memory cell. The refresh
signals rf and rfb are connected to the gates of M8 and M5 to
regenerate the states at nodes a1 and a2. The complementary
periodic refresh signals rf and rfb are used to regenerate the
states on nodes a1 and a2. As the read wordline is always
connected to the memory cell, then these two signals can be
used to control the pass gate transistors to block the feedback
loop.
Fig.5 shows the timing diagram of the proposed 13T memory
cell. When WL is high, the transistors M7 and M6 are on, and
the cell acts as a normal memory element. When WL is low, the
transistors M7 and M6 are off, and the feedback loop is cut off.
The refresh signals, rf and rfb, are generated by the read select
signal. When a column is selected for read, the rf and rfb
signals are generated by a complementary pulse generator to
refresh the data at the nodes a1 and a2 and ensure that the
correct signal is read by the bitline BL.
As the access transistors M1 and M2 are used for both (read
and write) operations, the refresh transistors M5 and M8 and
the refresh signals rf and rfb ensure a correct read operation. As
shown in Fig.5, when the memory stores “1” and a TF occurs,
node d can be restored, i.e. the TF will not propagate along the
feedback loop. When the memory stores “0” as data, a2 is “1”.
Consider the scenario in which a TF of large charge occurs on
node a2 and a small TF occurs on node d prior to the read
operation, thus driving node a2 to a “0” state and node d to a
“1” state. The state of node d will be temporarily changed to an
intermediate state (i.e. between “0” and “1”) because a2 is
unable to hold the state of node d. In this case, the state of node
a2 needs to be restored to drive node d to the correct state. Else,
during the read operation, M6 and M7 are on. The “0” state on
node a2 will change the data on nodes db and a1 to the “0” state,
resulting in a data change on d to a state “1” (its correct value is
“0”). If there is no refresh prior to the read operation, an error
occurs during the read operation if a TF strikes on node a2.
Therefore, the refresh signals rf and rfb generated by the read
select signal are connected to M8 and M5 to refresh the
memory cell before the read operation. The refresh operation is
performed by a pulse generator circuit sited at every column to

Page 5

> REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) <

5

Figure 6. Critical charge plot on the critical pair for DICE cell, 11T
hardened cell and 13T hardened cell
provide the refresh signal; once the column is accessed for a
read operation, the refresh signal is generated to refresh the
memory cells.
Simulation results using HSPICE show that adding the
refresh transistors and the refresh circuit to the proposed
hardened cell will only increase the average power
consumption by 0.8% of an individual memory cell during the
read access [10]. The power dissipation of this pulse generator
circuit (consisting of a dozen transistors) is very small and
therefore negligible compared to the entire memory array [10].
It is important to note that the read column select signal for
generating rf and rfb must arrive earlier than the read wordline.
This condition is always valid in the proposed design.
V. EVALUATION
In this section, different figures of merit as related to critical
charge, area, power dissipation and delay are assessed to
compare the proposed memory cell with other schemes found
in the technical literature.

Figure 7. Performance, power, and area comparison of the DICE, 11T and
13T cells
A. Multiple Node Upset Tolerance
The simulation of a multiple node upset starts with
indentifying the critical pair of the circuit. After finding the
critical pair of each memory cell, the curve of the primary node
charge versus the secondary node charge is plotted at 0.9V
power supply and room temperature. Compared to the 11T cell,
the 13T cell has one more node due to the two additional
transistors. As described in Section III.C, the number of
combinations for the 13T cell is 20. Simulation shows that the
same condition as for the 11T cell is also applicable to the 13T
cell, i.e. the critical pair of the 13T cell is still “a2 1->0, d 0->1”.
Fig.6 shows the simulation results for the single event scenario
with a multiple node upset. This plot is generated by HSPICE
simulation to provide a criterion to quantify the tolerance to a
multiple node upset, i.e. the area under the curve corresponds to
the tolerance. Any combination of charge in the node pair that
falls above (below) the curve will (not) result in an upset [12].
Therefore, a large area under the curve means a better tolerance
to a multiple node upset. It is also can be observed in Fig. 6 that
the curves do not intersect the X and Y axes, thus implying that
DICE, 11T, and 13T cells are tolerant to any single node upset
(i.e. when the charge deposited on one node is 0).
As shown in Fig.6, using the Schmitt trigger configuration,
the tolerance of a multiple node upset of the 13T cell is
improved significantly compared with the 11T memory cell.
The area under the curve is significantly increased compared
with the 11T cell, making it comparable to the area of the DICE
cell. In the 11T and 13T memory cells, the feedback loop is cut
off when the cell is holding data, therefore, when the charge on
the primary node is large enough to change the state of the
primary node, the tolerance to a single event causing a multiple
node upset of the memory cell is mostly determined by the
critical charge on the secondary node. As shown in Fig.6, the
Schmitt trigger configuration is employed in the 13T cell to
efficiently increase the critical charge on the secondary node.
Fig. 6 shows that the proposed 13T cell has better tolerance to a
single event when charge sharing is very diffused or limited in a
node pair (i.e. DICE will have better tolerance when charge
sharing/collection is nearly uniform), i.e. limited (diffused)
charge sharing corresponds to collection of a high (low) charge
at primary node and low (high) charge at secondary node. It has
been shown [13] that in practical designs and layouts, these are
the likely cases of occurrence at nanometric scale sizes.
B. Area, Power and Delay
The proposed hardened memory has thirteen transistors (13T)
compared to the memory cell of [10] with eleven transistors and
the DICE cell with twelve transistors. Additional transistors
consume more power depending on technology. In the
proposed hardened memory cell, the write operation can be
slowed down due to the transistors required for blocking the
feedback loop. In the 11T and 13T memory cells, the size of the
access transistors is therefore, increased to improve
performance.
The areas of the 11T hardened memory cell, the 12-transistor
hardened DICE memory cell, and the 13T hardened memory
cell are compared at 32nm CMOS technology (using the
predictive model data of [19] and MOSIS deep sub-micrometer
rules [20]). For fair comparison, the total width of the 11
transistors of the proposed cell is the same as the DICE
configuration (with 12 transistors). So, the width of the access
transistors M1 and M2 in Fig.4 is twice the width of the access