Multistage Planar Thermoelectric Microcoolers
ABSTRACT Many types of microsystems and microelectromechanical systems (MEMS) devices exhibit improved performance characteristics when operated below room temperature. However, designers rarely pair such devices with integrated cooling solutions because they add complexity to the system and often have power consumption which far exceeds that of the microsystem itself. We report the design, fabrication, and testing of both one- and six-stage thermoelectric (TE) microcoolers that target MEMS applications through optimization for low-power operation. Both coolers use thin-film Bi2Te3 and Sb2Te3 as the n-and p-type TE materials, respectively, and operate in a planar configuration. The six-stage cooler has demonstrated a ΔT = 22.3 °C at a power consumption of 24.8 mW, while the one-stage cooler has demonstrated a ΔT = 17.9 °C at a lower power consumption of 12.4 mW.
[show abstract] [hide abstract]
ABSTRACT: Micro cryogenic coolers can be used to cool small circuitry and improve their performance. The authors present a variety of micro coolers which are fabricated using MEMS technology production processes only. The typical dimension of a micro cold stage is 30 × 2.2 × 0.5 mm. It cools down to 96 K, applying Joule–Thomson expansion in a 300 nm high flow restriction and has a cooling power ranging from 10 mW to 25 mW. This paper discusses the operation of the micro cold stage and the characterization measurements done.Journal of Micromechanics and Microengineering 09/2007; 17(10):1956. · 2.11 Impact Factor
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ABSTRACT: The present work reports on the fabrication and characterization of a planar Peltier cooler on a flexible substrate. The device was fabricated on a 12 µm thick Kapton(c) polyimide substrate using Bi 2 Te 3 and Sb 2 Te 3 thermoelectric elements deposited by thermal co-evaporation. The cold area of the device is cooled with four thermoelectric junctions, connected in series using metal contacts. Plastic substrates add uncommon mechanical properties to the composite film–substrate and enable integration with novel types of flexible electronic devices. Films were deposited by co-evaporation of tellurium and bismuth or antimony to obtain Bi 2 Te 3 or Sb 2 Te 3 , respectively. Patterning of the thermoelectric materials using lift-off and wet-etching techniques was studied and compared. The performance of the Peltier microcooler was analysed by infrared image microscopy, on still-air and under vacuum conditions, and a maximum temperature difference of 5 • C was measured between the cold and the hot sides of the device.J. Micromech. Microeng. 01/2007; 17:168-173.
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ABSTRACT: SiGe/Si superlattice micro-coolers are investigated experimentally. They can be monolithically integrated with Si-based microelectronic devices to achieve localised cooling and temperature control. Cooling by as much as 4.2 K at 25°C and 12 K at 200°C was measured on 3 μm thick. 60×60 μm<sup>2</sup> devices. This corresponds to maximum cooling power densities approaching kW/cm <sup>2</sup>Electronics Letters 02/2001; · 0.96 Impact Factor
JOURNAL OF MICROELECTROMECHANICAL SYSTEMS, VOL. 20, NO. 5, OCTOBER 20111201
Multistage Planar Thermoelectric Microcoolers
Andrew J. Gross, Gi Suk Hwang, Baoling Huang, Hengxi Yang, Niloufar Ghafouri, Student Member, IEEE,
Hanseup Kim, Member, IEEE, Rebecca L. Peterson, Member, IEEE, Ctirad Uher,
Massoud Kaviany, Fellow, ASME, and Khalil Najafi, Fellow, IEEE
Abstract—Many types of microsystems and microelectro-
mechanical systems (MEMS) devices exhibit improved perfor-
mance characteristics when operated below room temperature.
However, designers rarely pair such devices with integrated cool-
ing solutions because they add complexity to the system and often
have power consumption which far exceeds that of the microsys-
tem itself. We report the design, fabrication, and testing of both
one- and six-stage thermoelectric (TE) microcoolers that target
MEMS applications through optimization for low-power opera-
tion. Both coolers use thin-film Bi2Te3and Sb2Te3as the n- and
p-type TE materials, respectively, and operate in a planar configu-
ration. The six-stage cooler has demonstrated a ΔT = 22.3◦C at
a power consumption of 24.8 mW, while the one-stage cooler has
demonstrated a ΔT = 17.9◦C at a lower power consumption of
12.4 mW. [2011-0087]
Index Terms—Microcooler, microelectromechanical systems
(MEMS), solid-state cooling, thermoelectric (TE) devices.
Manuscript received March 22, 2011; revised June 8, 2011; accepted
July 7, 2011. Date of publication August 30, 2011; date of current version
September 30, 2011. This work was supported by the Micro Cryogenic
Coolers Program of the Defense Advanced Research Projects Agency under
Grant W31P4Q-06-1-001. Portions of this work were performed at the Lurie
Nanofabrication Facility, a member of the National Nanotechnology Infrastruc-
ture Network, which is supported in part by the National Science Foundation.
The work of M. Kaviany was also supported by the World Class University
program through the National Research Foundation of Korea, Ministry of
Education, under Grant R31-30005. Subject Editor C.-J. Kim.
A. J. Gross was with the Electrical Engineering and Computer Science
Department, University of Michigan, Ann Arbor, MI 48109 USA. He is now
with Sandia National Laboratories, Albuquerque, NM 87185 USA (e-mail:
G. S. Hwang was with the Mechanical Engineering Department, University
of Michigan, Ann Arbor, MI 48109 USA. He is now with the Environmen-
tal Energy Technologies Division, Lawrence Berkeley National Laboratory,
Berkeley, CA 94720 USA (e-mail: firstname.lastname@example.org).
B. Huang was with the Mechanical Engineering Department, University of
Michigan, Ann Arbor, MI 48109 USA. He is now with the Department of Me-
chanical Engineering, The Hong Kong University of Science and Technology,
Kowloon, Hong Kong (e-mail: email@example.com).
H. Yang and C. Uher are with the Physics Department, University
of Michigan, Ann Arbor, MI 48109 USA (e-mail: firstname.lastname@example.org;
N. Ghafouri, R. L. Peterson, and K. Najafi are with the Electrical Engineer-
ing and Computer Science Department, University of Michigan, Ann Arbor,
MI 48109-2122 USA (e-mail: email@example.com; firstname.lastname@example.org;
H. Kim was with the Electrical Engineering and Computer Science Depart-
ment, University of Michigan, Ann Arbor, MI 48109 USA. He is now with the
Electrical and Computer Engineering Department, The University of Utah, Salt
Lake City, UT 84112 USA (e-mail: email@example.com).
M. Kaviany is with the Mechanical Engineering Department, University of
Michigan, Ann Arbor, MI 48109 USA, and also with the Division of Advanced
Nuclear Engineering, Pohang University of Science and Technology, Pohang
790-784, Korea (e-mail: firstname.lastname@example.org).
Color versions of one or more of the figures in this paper are available online
Digital Object Identifier 10.1109/JMEMS.2011.2163302
vices, such as resonators, gyroscopes, infrared sensors, and
low-noise amplifiers, which exhibit enhanced performance
when operated at temperatures below ambient. Resonant
MEMS, in particular, have very low power dissipation, and
many of the applications that integrate them seek to exploit
these low-power features as well as their small size . As a
result, any cooling device designed for integration with these
low-power MEMS devices should itself be both low power and
One approach to microscale cooling has been the develop-
ment of miniaturized Joule–Thompson (J–T) coolers –.
Some of these devices have effectively produced temperature
differentials of 192 K with heat loads up to 16 mW, using a
heat exchanger with a size of 2 mm × 35 mm × 1 mm .
However, the heat exchanger alone does not define a complete
J–T cooling system. J–T coolers also require a source of com-
pressed gas, which can be supplied by an external pressurized
source  or by an attached compressor . The lack of small
simple implementation makes J–T coolers impractical for many
Thermoelectric (TE) cooling, although less efficient than J–T
cooling, relies on solid-state operating principles that can be
scaled to the microdomain. As a result, TE cooling can be
effectively utilized in applications that require small, simple,
and robust coolers. Additionally, TE materials can be deposited
and patterned at the wafer level with standard microfabrica-
tion techniques, making batch-mode production a possibility.
Microscale TE coolers have been previously demonstrated by
several groups – representing a wide range of choices
in cooler design, TE materials, and fabrication techniques. A
summary of devices from industry and academia is provided
in Table I. The best performing coolers in this group are
able to generate temperature differentials between 40 K and
100 K; however, they require power inputs of several hundred
milliwatts or more. Such high power consumption makes these
coolers incompatible with MEMS integration in many applica-
tions. On the other hand, the low-power coolers to date have
not demonstrated enough total temperature differential to be
useful in achieving meaningful performance gains from the
target electronics and MEMS devices. This paper presents a
TE microcooling solution that can generate reasonably large
temperature differences with very small power.
The special features of micro TE coolers, including size ef-
HE NEED for microscale coolers is driven by micro-
electromechanical systems (MEMS) and electronic de-
1057-7157/$26.00 © 2011 IEEE
1202 JOURNAL OF MICROELECTROMECHANICAL SYSTEMS, VOL. 20, NO. 5, OCTOBER 2011
PREVIOUS WORK IN TE MICROCOOLERS
The maximum temperature difference that a thermocouple
(TC) can achieve in the absence of parasitic effects is given
ΔTmax≡ (Th− Tc)max=ZT2
where Tcis the cold junction temperature and Z is the TE figure
of merit for a pair of materials, i.e.,
where κt is the thermal conductivity, αS,i is the Seebeck
coefficient, and ρe,iis the electrical resistivity (i indicates the
p- or n-type material). For the case where the n- and p-type
materials have identical material properties with the exception
of the sign of the Seebeck coefficient, the figure of merit
By itself, (1) does not indicate any influence of scaling on the
performance of the cooler. All properly proportioned coolers
can theoretically reach the maximum ΔT described in (1).
However, the current needed to achieve ΔTmaxfor a given set
of materials does scale with the dimension of the cooler. The
current needed to reach ΔTmaxis
resistance of one TE pair (or TC). In a vertical cooler, Reis
proportional to δTE, the thickness of the TE films. As a result,
the power consumption at Ioptand ΔTmaxbecomes
optRe+ 2αSIoptΔT =2α2
where ATE is the cross-sectional area of the TC. From (5),
we note that the power consumption at ΔTmaxscales inversely
with the aspect ratio of the TE elements δTE/ATE. Therefore,
coolers with a high temperature differential and low power
consumption require TE elements with a high aspect ratio.
Achieving high aspect ratios with thin films requires a planar
design that transports heat laterally in the plane of the film,
instead of vertically through the film. This orientation of the
TCs allows for lithographic definition of the TE aspect ratio and
makes TE elements of arbitrary design possible. This stands in
contrast to the vertical design where the maximum aspect ratio
is limited by the maximum film thickness and the minimum lat-
eral feature size. While using a lateral design makes low-power
design with thin-film TE materials a possibility, the achievable
temperature differential is still limited by the figures of merit of
the materials being used. To overcome this limitation, multiple
stages can be employed . A multistage cooler should meet
three basic criteria in order to be effective. First, as with a
single-stage cooler, there must be low thermal conductance
across each stage. Second, the first stage (the warmest) must
have a higher heat removal capacity than the second stage,
the second stage must have a higher heat removal capacity
than the third, and so on. This is necessary because the Joule
heating that occurs in a given stage acts as a thermal load on
all the stages below it. For example, in a two-stage cooler,
the second stage experiences only the thermal load dissipated
by the device being cooled. Stage one, on the other hand,
experiences a thermal load equivalent to the power dissipated in
the target device plus the power dissipated in the second stage
of the cooler. It must therefore be able to remove more heat
than the second stage. Finally, there must be a high thermal
conductance between consecutive stages. This is necessary to
evenly distribute the heat transported into the interstage region
by the higher stage to all the TCs of the lower stage. At
the macroscale, a typical structure used to realize multistage
coolers is a vertical pyramid, with the coldest stage at the peak
. The shape arises naturally from the need for more cooling
power at the lower stages. The bulk TE material forms the
structure of the pyramid, eliminating the need for any addi-
tional materials to span stages and minimizing parasitic thermal
conduction. A high-thermal-conductivity ceramic is used as the
thermally conductive interstage material. This technique has
seen limited but effective implementation at the microscale
with devices demonstrating ΔTmax= 102 K . However,
we estimate that these vertical structure devices consume a
minimum of 5.3 W. This estimate is based on resistive losses
in the TE materials using the resistivity figures published in
 and the dimensions and currents given in . As with
a single-stage cooler, adapting the multistage design to a planar
structure will allow for a decrease in power consumption of up
to two orders of magnitude. Therefore, we have implemented
a multistage architecture using a planar design by arranging
GROSS et al.: MULTISTAGE PLANAR THERMOELECTRIC MICROCOOLERS1203
TE PROPERTIES AND DEPOSITION CONDITIONS
the stages in a series of concentric rings (or polygons), with
the coldest stage at the center. The remainder of this paper
will discuss the materials and microstructures used to realize
a planar multistage TE microcooler, investigate the impact
of parasitic effects on the performance of multistage planar
coolers, and present test results from several different cooler
II. MATERIALS AND DEPOSITION
At the macroscale, the TE materials of choice for cooling
in the range of 300 K are ternary and quaternary alloys
of (Bi,Sb)2(Te,Se)3, sometimes with additional dopants.
In bulk form, these materials have been produced with
demonstrated ZT at 298 K as high as 1.26 for p-type
(Bi0.25Sb0.75)2Te3doped with excess tellurium and 1.19 for
n-type Bi2(Te0.94Se0.06)3doped with iodine and excess tel-
lurium . Thin films of (Bi,Sb)2(Te,Se)3 with uniform
composition can be deposited by a variety of methods, includ-
ing electroplating , sputtering , and coevaporation ,
. These techniques have produced TE materials with ZT
values that approach those found in bulk materials of similar
composition. Recently, superlattice materials consisting of al-
ternating layers of various (Bi,Sb)2(Te,Se)3compounds have
been deposited by metal–organic chemical vapor deposition,
yielding ZT values as high as 2.4 for n-type material and
1.4 for p-type material . For this project, coevaporated
binary compounds were utilized. The materials were deposited
on heated substrates from independently controlled elemental
sources to achieve near-stoichiometric films. The films have
been previously characterized, and the parameters of deposition
have been optimized for maximum ZT . The deposition
conditions and resulting film properties are summarized in
Table II. The n-type Bi2Te3 has a ZT of 0.43, while the
p-type Sb2Te3has a ZT of 0.39, both of which are comparable
to properties achieved by others in binary thin films.
III. STRUCTURE AND FABRICATION
To create a planar multistage TE microcooler, a microfab-
ricated structure was developed which meets the criteria for
effective multistage cooling. The cooler is shown in Fig. 1. It
utilizes a multiwafer stack of silicon and glass. The two sub-
strates are processed in parallel and are then bonded together to
form the completed cooler.
its major components, including the isothermal silicon islands, insulating
dielectric, supporting glass, and TE elements.
Three-dimensional rendering of the six-stage TE microcooler showing
100-μm-thick silicon wafer. (b) Cross-sectional view of (middle) “structural
substrate,” which contains a suspended glass tether used to support the cold
stage. (c) Cross-sectional view of the completed cooler.
(a) Cross-sectional view of the “thermal substrate” fabricated from a
A. Thermal Substrate
The top substrate in the stack is fabricated from a thin silicon
wafer and implements the necessary thermal properties for a
multistage cooler. The interstage regions are made of silicon,
which has high enough thermal conductivity to make these
regions isothermal. In the vertical pyramid design, only the TE
materials span the space between the isothermal interstage lay-
ers. Thin-film planar TE coolers require an additional material
to span this gap and mechanically support the TE films. Here,
we use a thin dielectric membrane to serve this function without
creating a large parasitic heat path between stages. The top
substrate is fabricated using the following steps, as shown in
1204JOURNAL OF MICROELECTROMECHANICAL SYSTEMS, VOL. 20, NO. 5, OCTOBER 2011
(c) the Version-2 six-stage cooler, with a different isothermal island spacing and a different TE element configuration from (b). The insets highlight the TE
elements and oxide bridges.
Top-down micrographs of (a) a one-stage cooler, (b) the Version-1 six-stage cooler with visible cold stage, isothermal islands, and TE elements, and
1) A thin film of silicon dioxide is deposited on the top
surface of the wafer and patterned by etching in buffered
2) A layer of Cr/Au is deposited on top of the oxide layer
and patterned using lift-off.
3) A 30-μm recess is etched in the back side of the wafer
using deep reactive ion etching (DRIE).
4) A second DRIE step creates deep through-wafer trenches
that stop on the SiO2 layer. The trench etching forms
concentric squares of silicon separated by oxide bridges,
as shown in Fig. 3.
5) Both the front and back sides of the wafer are cleaned
B. Structural Substrate, Bonding, and TE Deposition
Because the resulting thermal substrate is relatively fragile,
a second substrate, referred to here as the structural substrate,
is fabricated to provide additional mechanical support without
sacrificing overall thermal isolation. The support is provided
by a thin glass tether, which is bonded to the center of the
cooler and/or selected isothermal rings. This tether is fabricated
and integrated with the rest of the cooler using the following
process, shown in Fig. 2(b) and (c).
1) A shallow recess is etched in the top side of a 500-μm-
thick silicon wafer using DRIE.
2) A 100-μm-thick Pyrex glass wafer is bonded to the top
side of the silicon wafer, covering the recess.
3) A layer of Cr/Au is deposited over the glass and patterned
to form a masking layer.
4) The glass wafer is etched in a concentrated HF solution,
and the masking metal layer is stripped.
5) The thermal substrate is aligned to the structural sub-
strate, and they are anodically bonded.
6) A shadow mask is aligned to the device wafer and
clamped into place. The Bi2Te3 film is deposited by
coevaporation at a substrate temperature of 260◦C.
7) The shadow mask is switched, and Sb2Te3is deposited at
Shadow mask patterning is chosen as the last fabrication
step to avoid wet and dry processes which might damage
the fragile cooler, be incompatible with the TE deposition
temperatures, or contaminate silicon processing tools.
DESIGN PARAMETERS FOR SIMULATED ONE- AND SIX-STAGE COOLERS
Fig. 3 shows a six-stage cooler along with a one-stage cooler
fabricated through the same process, omitting the glass tether.
IV. MODELING AND DESIGN
To understand multistage coolers and the effect of
nonidealities—such as the thermal conduction of the dielectric
membrane and contact resistance—on their performance, a 1-D
model was developed. One- and six-stage coolers were simu-
lated. The model takes into account all the major TE effects,
including Peltier heat transfer, Joule heating from the TE thin
films and from contact resistance, and thermal conduction .
The model was initially implemented using Matlab and has also
been ported to Mathematica. The simulated one-stage cooler
and the first stage of the six-stage cooler were identical and
measured 5.4 mm on a side, with a total of 64 TCs. The
geometry of the TCs, the number of TCs at each stage of the
six-stage design, and the size of each of the stages are given in
The material properties used in the simulations are in
Table II. The devices were simulated both with and without
the supporting oxide required for the actual device, and in each
case, they were simulated once with no contact resistivity (Rc)
and once with a high contact resistivity Rc= 1.24 × 10−8Ω ·
m2. This latter value was chosen because it is the resistivity at
which the contact resistance of one TC is equal to the intrinsic
resistance of the TC. Fig. 4 shows the cooling generated using
different input currents, i.e., with different input powers. In
the ideal case, with no oxide and no contact resistance, the
GROSS et al.: MULTISTAGE PLANAR THERMOELECTRIC MICROCOOLERS1205
contact resistivities. Both are shown with and without a 1.5-μm-thick supporting oxide, with contact resistivities of 0 and 1.24 × 10−8Ω · m2. The latter value,
1.24 × 10−8Ω · m2, corresponds to the point where the contact resistance is equal to the TE material resistance for one TC.
one-stage cooler is predicted to reach 255.1 K from an ambient
temperature of 300 K at a power of more than 200 mW,
while the six-stage cooler reaches 202.9 K using less than
100 mW, making the potential benefit of multistage cooling
However, when simulated with the supporting oxide mem-
brane and the elevated contact resistance, the coolers only
reach 281.8 K and 272.9 K for the one- and six-stage devices,
respectively. In the ideal case, the six-stage cooler achieved a
temperature differential more than twice as large as that of the
one-stage cooler; however, in the more realistic case, the six-
stage cooler was only able to achieve a 49% greater temperature
differential, indicating that the effects of contact resistance and
the supporting oxide negate some of the benefits of adding
multiple stages. To further investigate the parasitic effects of
the supporting oxide and contact resistivity, the devices were
simulated over a wide range of contact resistivities both with
and without the supporting oxide. At each value of contact
found. The results are shown in Fig. 5. With a negligible contact
resistivity of 1 × 10−11Ω · m2and no oxide, the simulated
performance of the coolers is the same as that discussed pre-
viously in the first case. The effect of contact resistivity is min-
imal for values less than 1 × 10−9Ω · m2. Above this, cooler
performance rapidly decreases and is significantly degraded at
Rc= 1 × 10−7Ω · m2. The minimum achievable cold stage
temperature slowly approaches 300 K as contact resistance
A similar trend is seen in the devices simulated with a
1.5-μm-thick layer of oxide to support the TE material (Fig. 5).
The results clearly indicate that thermal conduction through
the supportive oxide partially negates the benefits of multiple
stages. At the lowest contact resistivity, the one- and six-stage
coolers reach 265.1 K and 248.2 K. While there is still a
performance gain achieved by using multiple stages, the
one-stage cooler in this case achieves a temperature differential
that is 67% of that achieved by the six-stage cooler. In the
ideal case without oxide, the one-stage cooler only achieves
Predicted thermal performances of (a) a one-stage cooler and (b) a six-stage cooler, with respect to power consumption for two oxide thicknesses and two
simulated as a function of the contact resistivity. Both cooler designs are
simulated under ideal conditions with no oxide supporting the TE material and
under realistic conditions with 1.5 μm of oxide. The TE material properties
and geometric parameters used in the simulations can be found in Tables II
Variation in thermal performance of one- and six-stage coolers
a temperature differential that is 48% of that of the six-stage
design, as noted earlier.
The limited gain of additional stages in nonideal cooler
performance is likely due to high relative parasitic losses
through the oxide at the highest (coldest) stages. In stages 4,
5, and 6, only a few TE elements cross a dielectric bridge
that is effectively several millimeters wide. The total thermal
conduction though the dielectric membrane will be several
times greater than the thermal conduction through the TE. This
leads to a decrease in the effective Z, limiting the benefit from
these stages. In contrast, the outer stages have a large number of
order of magnitude as or smaller than the conduction through
Despite the limiting effect of parasitic thermal conduction, a
multistage design is still desirable because of its effect on the
cooler efficiency per degree of cooling. The six-stage cooler
1206JOURNAL OF MICROELECTROMECHANICAL SYSTEMS, VOL. 20, NO. 5, OCTOBER 2011
one- and six-stage coolers, taking into consideration contact resistivity of 1.24 × 10−8Ω · m2and a 1.5-μm-thick layer of oxide supporting the TE material.
demonstrates a temperature differential per milliwatt that is at
least one order of magnitude greater than that of the one-stage
cooler when both are operated at the same temperature differ-
ential. This is shown in Fig. 6. Under the ideal assumptions, the
one-stage cooler is predicted to use 264 mW at its maximum
ΔT of 45 K. At this same ΔT, the six-stage cooler only
uses 4.2 mW. Similarly, with the oxide and contact resistivity
included, the one-stage cooler would use 148 mW to achieve
a temperature difference of 19.5 K, while the six-stage cooler
only uses 7.3 mW of power to reach the same result.
(a) Predicted degree of cooling per milliwatt as function of cooling for ideal one- and six-stage coolers. (b) Predicted degree of cooling per milliwatt for
V. TESTING AND ANALYSIS
To experimentally verify these simulation results, two ver-
sions of a six-stage cooler plus a one-stage cooler were fab-
ricated and tested. The parameters used to fabricate all three
devices are outlined in Table IV, and the devices are shown in
Fig. 3. The primary difference between the two 6-stage designs
lies in the size and layout of the contact areas and in the
perimeters of the stages, which were adjusted to accommodate
the modified contact layout. The goal behind the layout of
Version 2 was to minimize the overall resistance of the cooler
using geometric changes to reduce contact effects. The size
of the contact area was increased from 100 μm × 100 μm to
100 μm × 200 μm. In addition, as shown in Fig. 3(c), Version 2
makes use of long segments of TE material that span several
stages. This eliminates the need for the current to travel from
the TE to the metal and back at every TC in every stage. Finally,
by making the silicon somewhat narrower in the stages where
this technique is employed, the total resistance of the device
can be decreased. The design improvement was confirmed by
measurement: The Version-2 cooler has a total series resistance
of 816 Ω when operated at its optimal point compared to 977 Ω
for the Version-1 cooler, despite the Version-1 cooler having a
larger average TE film thickness.
The coolers were tested in a vacuum probe station at a
pressure of less than 0.133 Pa (1 mTorr). The temperature
was measured using a resistive element in a four-point probe
configuration. Fig. 7 shows the results from both versions of
the six-stage cooler and the single-stage cooler. Version 1 gen-
DESIGN PARAMETERS FOR FABRICATED ONE- AND SIX-STAGE COOLERS
versions of the six-stage cooler and the one-stage cooler. Material properties
were used as simulation parameters to fit the model to the measured results.
(Symbols) Measured versus (lines) modeled performance of both
erated a temperature differential of 16.6 K with an input power
24.4 mW, while Version 2 generated a differential of 22.3 K
with an input power of 24.8 mW.
The model described earlier was then fit to the data to
estimate the average properties of the in situ materials. The See-
beck coefficient, thermal conductivity, and the combined effect
of contact resistance and film resistance were used as the fitting
parameters. To perform the fit, contact resistance was first fit
to a value of 1.03 × 10−8Ω · m2to adjust the total resistance
of the simulated cooler to the measured resistance of the actual
cooler, assuming a resistivity of 20 μΩ · m for both TE films.
This assumption is valid because the important parameter is the
GROSS et al.: MULTISTAGE PLANAR THERMOELECTRIC MICROCOOLERS1207
load conditions. In all cases, the ambient temperature is maintained at 300 K, and the temperature of the center region is increased by applying a thermal load with
a resistive element. (a) Results from a one-stage cooler, along with curves fitted to the physical model. (b) Results from a six-stage cooler.
(Left axes) Optimum input current and (right axes) change in temperature between the OFF and ON states at the center of the cooler under varying thermal
with the described method. Note that the fitted value of contact
resistivity is below the critical value of 1.24 × 10−8Ω · m2
used in the modeling in Section IV and compares favorably
with others’ measured values reported in , , , ,
and –. Next, it is assumed that both the p- and n-type
materials have the same Seebeck coefficient magnitude, which
is adjusted so that the measured optimum current matches
the simulated value. Finally, the thermal conductivity of the
TE material is adjusted to match the magnitude of the max-
imum simulated ΔT with the measured results. The model
used included the SiO2 membrane, which was assumed to
have a thermal conductivity of 1.15 W/(m · K). For Version 1
of the six-stage cooler, the estimated Seebeck coefficient
was 180 μV/K, and the estimated thermal conductivity was
1 W/(m · K). Version 2 also indicated a thermal conductivity
of 1 W/(m · K), but its Seebeck coefficient was lower at
166 μV/K. This variation in TE material properties is likely
due to inaccurate control of material flux rates and substrate
temperature inside the deposition chamber. To understand how
the structure of the cooler affected the overall results, the
ideal model was fitted to the data and used to calculate an
effective Z. In effect, this calculation poses the question: In
the absence of parasitic thermal conductance and Joule heating,
what figure of merit would produce a six-stage cooler with the
measured performance curve? The performance of Version 1
is replicated using a TE material with an effective Z of 1.6 ×
10−4K−1, corresponding to an effective ZT of 0.048 at 300 K.
Version 2 fared slightly better, requiring material with an ef-
fective Z of 2.2 × 10−4K−1or an effective ZT of 0.066 at
300 K. However, both effective ZT values are low compared
to the intrinsic material properties shown in Table II. This
indicates that the TE material is not being effectively utilized
in these coolers. As already discussed, this is most likely due to
the supportive oxide used in the inner stages.
The one-stage cooler was able to achieve a temperature
differential of 17.9 K at a current input of 8.5 mA, as shown in
Fig. 7. The effective Z was calculated for the one-stage cooler
to be 4.6 × 10−4K−1, corresponding to a ZT of 0.13. While
significantly closer to the measured intrinsic value, this low
number indicates that the performance of the one-stage cooler
is also hampered by parasitic effects due to contact resistance
and the presence of the oxide membrane. Using the same curve-
fitting technique described previously, the average Seebeck
coefficient was found to be 185 μV/K, again with an estimated
thermal conductivity of 1 W/(m · K). This Seebeck coefficient
is larger than the value found for the Version-2 six-stage
cooler described previously, even though both were fabricated
simultaneously on the same wafer. However, it has previously
been shown that the Seebeck coefficient of the coevaporated
thin films is closely related to the temperature of the substrate
during deposition . In the six-stage cooler, the center stages
are highly isolated from the substrate, and thus, the temper-
ature of the inner stages may vary from the temperature of
the outer stages and the single-stage cooler during deposition.
This likely degrades the quality of the material at the inner
stages. Parametric analysis of the one-stage cooler was used to
estimate the fitting error for material properties: ±2% for the
Seebeck coefficient, ±5% for the TE thermal conductivity and
TE resistivity, and ±10% for contact resistivity.
Finally, both the one- and six-stage designs were tested under
thermal loads. The resistive temperature sensor supplied loads
of varying magnitude. As the thermal load was raised, both
coolers were able to generate higher differences in temperature
between the OFF state and the optimum current (maximum ΔT)
point. In addition, both the coolers exhibited an increase in the
magnitude of the optimal current. With the cooler off, a 50-mW
resistive heating load was applied, raising the center of the
one-stage device to 450.3 K. When a current was applied,
Iopt was found to have increased to 12 mA, and the center
region was cooled to 415.0 K. This represents a change of
35.3 K, compared to only 18.0 K using an 8-mA current when
the device was loaded with 100 μW. Similarly, with a 25-mW
load, the six-stage device was able to reduce the temperature of
the cooler region from 494.9 K to 465.8 K, a change of 29.1 K
with an optimum current of 7 mA. This apparent improvement
in performance is a result of the temperature dependence of
ΔTmax, as described by (1). Fig. 8 shows this effect for both the
one- and six-stage coolers. The data from the one-stage cooler
1208JOURNAL OF MICROELECTROMECHANICAL SYSTEMS, VOL. 20, NO. 5, OCTOBER 2011
are shown in Fig. 8(a) along with curves fitted to the ideal cool-
ing equations. The change in temperature of the center stage is
fit to (1) and results in a calculated Z = 4.3 × 10−4± 2.6 ×
10−5K−1with a 95% confidence interval. This corresponds
to ZT of 0.13 ± 0.007, which is identical to the ZT value
calculated previously for the one-stage cooler. The relationship
between temperature and the optimum current was fit to (4) and
produced αS/Re= 2.87 × 10−5± 5 × 10−7A · K−1, which
fits the data with a sum-of-square error of 5.56 × 10−8. The
excellent fit suggests that the one-stage cooler obeys the ideal
equations (1)–(5). The data for the six-stage cooler are shown
in Fig. 8(b). However, because the six-stage cooler is more
complex, the aforementioned equations are too simplistic to
model the relationship between ΔT and Ioptand Tcenter, and it
is therefore difficult to extract a value of effective Z from these
Lower thermal loads were used to measure the thermal
resistance of the total structure. The one-stage cooler increased
its temperature by 2.7 K upon application of a 1-mW load,
leading to a calculated thermal resistance of 2700 K/W. This
implies that ΔT would be equal to zero when a 6.6-mW load
is applied. The one-stage cooler consumes 14.6 mW under
maximum cooling when a 10-mW load is supplied. Therefore,
the estimated coefficient of performance (COP) of the cooler
(the cooling capacity divided by the power consumption) at
ΔT = 0 is 0.45. The temperature of the center stage of a
Version-2 six-stage cooler tested under a 1-mW thermal load
increased by 8.9 K from a base temperature of 279.2 K. It uses
20.8 mW of power for maximum cooling under a 10-mW load.
This corresponds to a thermal resistance of 8900 K/W and a
2.3-mW load to achieve ΔT = 0. The approximate COP at
ΔT = 0 is 0.1.
This paper has demonstrated the feasibility of low-power TE
microcoolers and has demonstrated the first six-stage planar TE
microcooler. Cooling of 22.3 K relative to ambient has been
achieved with less than 25 mW of power input. While this is
not yet competitive with current commercial options in terms
of temperature differential, it uses an order of magnitude less
power per degree of cooling. Additionally, the investigation of
simulated coolers shows that there is a clear path to achieving
higher temperature differences and to realizing a higher degree
of differentiation between the one- and six-stage microcoolers.
This path includes reducing the parasitic resistance of the
cooler, particularly at the contacts, and removing as much of
the parasitic thermal conduction paths as possible, particularly
at the innermost stages.
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Giani, F.Pascal-Delannoy, and
Andrew J. Gross received the B.S. degree in electri-
cal engineering from Michigan Technological Uni-
versity, Houghton, in 2004, and the M.S. and Ph.D.
degrees in electrical engineering from the University
of Michigan, Ann Arbor, in 2007 and 2010, respec-
He is currently an Engineer with Sandia National
Laboratories, Albuquerque, NM.
Gi Suk Hwang received the B.S. degree in mechan-
ical and electrical engineering from Handong Global
University, Pohang, Korea, in 2002, and the M.S.
and Ph.D. degrees in mechanical engineering from
the University of Michigan, Ann Arbor, in 2006 and
He is currently a Postdoctoral Researcher with
the Environmental Energy Technologies Division,
Lawrence Berkeley National Laboratory, Berkeley,
CA, where he is working on a polymer electrolyte
membrane fuel cell. His research interests include
electrochemical catalysis, proton-conducting membrane, and atomic-level heat
transfer, including thermoelectrics, heat pipe, and pool boiling. He has pub-
lished 15 research papers in electrochemical/thermal science and engineering
Baoling Huang received the B.S. degree and the
M.S. degree in engineering thermophysics from
Tsinghua University, Beijing, China, in 1999 and
2001, respectively, and the Ph.D. degree in mechan-
ical engineering from the University of Michigan,
Ann Arbor, in 2008.
From 2001 to 2004, he worked in industry, and
from 2008 to 2010, he was a Postdoctoral Research
Fellow at the University of California, Berkeley,
and the Lawrence Berkeley National Laboratory,
Berkeley. Since 2010, he has been an Assistant
Professor in the Department of Mechanical Engineering, The Hong Kong
University of Science and Technology, Kowloon, Hong Kong. He has re-
search experience in both theoretical modeling and experimental fabrications/
measurements. His research interests include the broad area of energy transport,
conversion, and storage. His current research mainly focuses on developing
the fundamental understanding of energy transport and conversion in novel
nanoengineered thermoelectric materials.
Hengxi Yang received the B.S. degree in physics
from the University of Science and Technology of
China, Hefei, China, in 2007. He is currently work-
ing toward the Ph.D. degree in the Physics Depart-
ment, University of Michigan, Ann Arbor.
His current research focuses on understanding the
dynamics and confinement effect of polymers, as
well as the transport behaviors of charge carriers in
conjugated polymer systems.
Niloufar Ghafouri (S’00) received the B.S. de-
gree in electrical engineering from the University of
Tehran, Tehran, Iran, in 2002, and the M.S. degree
in electrical engineering systems with a major in
communications from the University of Michigan,
Ann Arbor, in 2004, where she is currently working
and Computer Science Department.
Her research interests include thin-film thermo-
electric materials development, processing, and ther-
moelectric energy harvesting.
Hanseup Kim (S’99–M’06) received the B.S. de-
gree (magna cum laude) in electrical engineering
from Seoul National University, Seoul, Korea, in
1997, and the M.S. and Ph.D. degrees in electrical
engineering from the University of Michigan, Ann
Arbor, in 2002 and 2006, respectively.
Between 2006 and 2009, he was a Postdoctoral
Research Fellow with the Center for Wireless In-
tegrated MicroSystems (WIMS) and the Electrical
Engineering and Computer Science Department at
the University of Michigan, where he worked on a
micro gas chromatography system, energy harvesting devices, micro hydraulic
actuators, and a micro cryogenic cooler. Since 2009, he has been a Utah Science
Technology and Research Initiative (USTAR) Assistant Professor of electrical
and computer engineering, mechanical engineering, and bioengineering at the
University of Utah, Salt Lake City. His present research at The University of
Utah focuses on the development of integrated microsystems for health care
research, including microfluidics, biosensors, microrobots, and heterogeneous
Dr. Kim was a recipient of the Best Paper Award with eight other coauthors
at the International Conference on Commercialization of Micro and Nano
Systems in 2008, the First Prize and the Best Paper Award with three other
coauthors at the 38th International Design Automation Conference in 2001, and
a Rotary Club Scholarship in 1999. He is on the Technical Program Committee
for the NanoUtah Conference (2010–2011 and 2011–2012).
Rebecca L. Peterson (S’98–M’06) received the B.S.
degree in electrical engineering from the University
of Rochester, Rochester, NY, in 1996, the M.S. de-
gree in electrical engineering from the University
of Minnesota–Twin Cities, Minneapolis and Saint
Paul, in 2000, and the Ph.D. degree in electrical
engineering from Princeton University, Princeton,
NJ, in 2006.
From 2006 to 2009, she was a Postdoctoral Re-
searcher with the Cavendish Laboratory, Department
of Physics, University of Cambridge, Cambridge,
U.K., where she was also an Associate Lecturer at Newnham College. Previ-
ously, she was with Guidant Corporation (now Boston Scientific), where she
worked on IC design for cardiac rhythm management products. Since 2009,
she has been an Assistant Research Scientist in the Electrical Engineering
and Computer Science Department, University of Michigan, Ann Arbor. Her
research interests include the fabrication and mechanical and electrical char-
acterization of semiconducting, thermoelectric, and piezoelectric materials and
their application in thin-film transistors and integrated microelectromechanical
systems on both hard and soft substrates.
Dr. Peterson was a recipient of the National Science Foundation Graduate
Fellowship in 1996, the Automatic RF Techniques Group Student Fellowship in
1999, and the American Association of University Women Selected Professions
Fellowship in 2004–2005.
1210 JOURNAL OF MICROELECTROMECHANICAL SYSTEMS, VOL. 20, NO. 5, OCTOBER 2011
Ctirad Uher received the B.Sc. and Ph.D. degrees
in physics from the University of New South Wales,
Sydney, Australia, in 1972 and 1975, respectively.
He is the C. Wilbur Peters Collegiate Professor of
Physics at the University of Michigan, Ann Arbor,
where he has been on the faculty since 1980 and
was the Director of the National Science Foundation-
funded Materials Research Group from 1986 to
1990, the Associate Dean for Research, Facilities,
and Computing from 1992 to 1994, and the Chair
of the Department of Physics from 1994 to 2004.
His research interests center on experimental studies of transport properties
and superconductivity in metals, semimetals, and layered materials, including
molecular-beam-epitaxy-grown artificial metallic superlattices and high-Tc
Dr. Uher has served as President, Vice-President, and Member of the
Board of Directors of the International Thermoelectric Society, has chaired
the International Thermal Conductivity Conference (1999), and is a member
of the organizing committee for the 2011 International Conference on Thermo-
electrics. He was a recipient of the Doctor Honoris Causa from the University
of Pardubice, Pardubice, Czech Republic, in 2002, and has been an Expert
Faculty Opponent at L’Institute National Polytechnique De Lorraine, Nancy,
France, in 1997 and 2002. He was also a recipient of the University of Michigan
College of Literature, Science and the Arts’ Excellence in Research Award and
Excellence in Teaching Award in 2000 and 2007, respectively. He is a Fellow
of the American Physical Society.
Massoud Kaviany received the Ph.D. degree from
the University of California, Berkeley, in 1979.
Since 1986, he has been with the University of
Michigan, Ann Arbor,where heis currently a Profes-
sor in the Mechanical Engineering Department and
in the Applied Physics Program. He is also with the
Division of Advanced Nuclear Engineering, Pohang
University of Science and Technology, Pohang,
Korea. He is the author of Heat Transfer Physics
(Cambridge University Press, 2008) and Essentials
Dr. Kaviany has been a Fellow of the American Society of Mechanical
Engineers (ASME) since 1992 and was the Chair of the ASME Committee on
Theory and Fundamental Research in Heat Transfer (1995–1998). He was the
recipient of the 2002 ASME Heat Transfer Memorial Award (Science) and the
2010 ASME Harry Potter Gold Medal (Thermodynamics Science). He was also
the recipient of the College of Engineering 2003 Education Excellence Award
from the University of Michigan.
Khalil Najafi (S’84–M’85–SM’97–F’00) received
the B.S., M.S., and Ph.D. degrees in electrical engi-
neering from the University of Michigan, Ann Arbor,
in 1980, 1981, and 1986, respectively.
He is the Schlumberger Professor of Engineering
in the Electrical Engineering and Computer Science
Department, University of Michigan, where has was
previously the Deputy Director of the National Sci-
ence Foundation (NSF) Engineering Research Cen-
ter on Wireless Integrated Microsystems, was the
Director of the Solid-State Electronics Laboratory
from 1998 to 2005, has been the Director of NSF’s National Nanotechnology
Infrastructure Network since 2004, and has been the Chair of the Electrical
and Computer Engineering Division since September 2008. His research
interests include micromachining technologies, micromachined sensors, ac-
tuators, and microelectromechanical systems; analog integrated circuits; im-
plantable biomedical microsystems; micropackaging; and low-power wireless
sensing/actuating systems. He has been active in the field of solid-state sensors
and actuators for 30 years. He has served as Associate Editor or Editor of
Dr. Najafi is a Fellow of the American Institute for Medical and Biological
Engineering. He has been involved in several conferences and workshops
dealing with microsensors, actuators, and microsystems, including the Inter-
national Conference on Solid-State Sensors and Actuators, the Hilton-Head
Solid-State Sensors and Actuators Workshop, and the IEEE/ASME Micro
Electromechanical Systems Conference.