Analysis and Design of Energy and Slew Aware Subthreshold Clock Systems

Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (Impact Factor: 1.2). 10/2011; DOI: 10.1109/TCAD.2011.2144595
Source: IEEE Xplore

ABSTRACT In this paper, we analyze the effect of clock slew in subthreshold circuits. Specifically, we address the issue that variations in clock slew at the register control can cause serious timing violations. We show that clock slew variations can cause frequency targets to deviate by as much as 28% from the design goals. Based on these observations, we recognize the importance of clock slew control in subthreshold circuits. We propose a systematic approach to design the clock tree for subthreshold circuits to reduce the clock slew variations while minimizing the energy dissipation in the tree. The combined approach, including the wire sizing and dynamic nodal capacitance control, can achieve better slew control (and better timing control) at lower energy in subthreshold circuits.

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    ABSTRACT: This paper presents a design methodology for robust and low-energy clock networks for ultra-low voltage (ULV) circuits. We show that both clock slew and skew play important roles in achieving high maximum operating frequency (Fmax) and low clock energy in ULV circuits. In addition, clock networks in ULV circuits are highly sensitive to process variations. We propose a variation-aware methodology that controls both clock skew and slew to maximize Fmax and minimize clock power. Experimental results show that our clock network design method achieves lower energy (more than 20 % savings) at comparable or even higher Fmax compared with the existing methods. Keywords—clock network design, ultra-low voltage, robustness for automated synthesis of robust (low-slew and low-skew) and low- energy clock network. In this paper, we develop a variation-aware methodology for robust and low-energy clock network design for ultra-low voltage circuits. The contributions of this paper are as follows.  We present a comprehensive study based on extensive experi- mental results that show the impact of clock skew and clock slew control on power consumption, performance, and variation tolerance in ultra-low voltage (ULV) circuits.  We develop a variation-aware ULV clock network design methodology. For clock skew management, we construct the routing topology and insert buffers to minimize the delay differ- ences among the clock paths under both nominal and statistical conditions. We also show how to efficiently control clock slew bound at each sink under both nominal and statistical conditions. Our algorithm generates and saves multiple solutions to achieve minimum clock energy.  Experimental results show that our clock design method is able to efficiently control the clock skew and slew in both nominal and statistical conditions, and construct ULV clock networks with low clock energy at a high maximum operating frequency. We outperform state-of-the-art ULV clock routing methods (2), (5) in terms of performance and energy under both nominal and statistical conditions.
    Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010, Austin, Texas, USA, August 18-20, 2010; 01/2011

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