Programmable analog device array (PANDA): A platform for transistor-level analog reconfigurability

Abstract

The design and development of analog/mixed-signal (AMS) ICs is becoming increasingly expensive, complex, and lengthy. Lacking a reconfigurable platform, analog designers are denied the benefits of rapid prototyping, hardware emulation, and smooth migration to advanced technology nodes. To overcome these limitations, this work proposes a new approach that maps any AMS design problem to a transistor-level reconfigurable vehicle, thus enabling fast validation and a reduction in post-Silicon bugs, and minimizing design risk and costs. The unique features of the approach include: (1) transistor-level programmability that emulates each transistor behavior in an analog design, reproducing the system and achieving very fine granularity of reconfiguration; (2) programmable switches that are treated as a design component during analog transistor mapping, and optimized with the reconfiguration matrix; (3) parasitics reduction that leverages the aggressive scaling of CMOS technology. Based on these principles, a digitally controlled PANDA platform is designed at a 32nm node. Several 90nm analog blocks are successfully emulated with the 32nm platform, including a folded-cascode operational amplifier, a sample-and-hold module (S/H), and a voltage-controlled oscillator (VCO). A solid basis to future efforts on the architecture, hierarchical optimization, and related design automation tools is demonstrated.