Low-Frequency Noise Characterization of Strained Germanium pMOSFETs
ABSTRACT Low-frequency noise in strained Ge epitaxial layers, which are grown on a reverse-graded relaxed SiGe buffer layer, has been evaluated for different front-end processing conditions. It has been shown that the 1/ f noise in strong inversion is governed by trapping in the gate oxide (number fluctuations) and not affected by the presence of compressive strain in the channel. However, some impact has been found from the type of halo implantation used, whereby the lowest noise spectral density and the highest hole mobility are obtained by replacing the standard As halo by P implantation. At the same time, omitting the junction anneal results in poor device characteristics, which can be understood by considering the presence of a high density of nonannealed implantation damage in the channel and the gate stack near the source and the drain.
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ABSTRACT: In this paper, the dispersion relationship is derived by using the k · p method with the help of the perturbation theory, and we obtain the analytical expression in connection with the deformation potential. The calculation of the valence band of the biaxial strained Ge/(001)Si1−xGex is then performed. The results show that the first valence band edge moves up as Ge fraction x decreases, while the second valence band edge moves down. The band structures in the strained Ge/ (001)Si0.4Ge0.6 exhibit significant changes with x decreasing in the relaxed Ge along the [0, 0, k] and the [k, 0, 0] directions. Furthermore, we employ a pseudo-potential total energy package (CASTEP) approach to calculate the band structure with the Ge fraction ranging from x = 0.6 to 1. Our analytical results of the splitting energy accord with the CASTEP-extracted results. The quantitative results obtained in this work can provide some theoretical references to the understanding of the strained Ge materials and the conduction channel design related to stress and orientation in the strained Ge pMOSFET.Chinese Physics B 01/2012; 21(5). · 1.39 Impact Factor
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ABSTRACT: The aim of this review paper is to describe the impact of so-called border traps (BTs) in high- k gate oxides on the operation and reliability of high-mobility channel transistors. First, a brief summary of the physics of BTs will be given, describing the charge trapping and release in terms of the elastic tunneling model. It will be also pointed out how information on the BT properties can be extracted from popular measurement techniques such as low-frequency (1/f) noise and variable-frequency charge pumping. In the next two parts, the impact of BTs on metal-oxide-semiconductor structures fabricated on Ge or III-V channel materials is outlined, with particular emphasis on the development of novel or adapted measurement techniques such as AC transconductance dispersion or trap spectroscopy by charge injection and sensing. Finally, the effect of BTs on the operation and reliability of high-mobility channel MOSFETs is discussed. It is also shown that the density of BTs is closely linked to the quality or defectivity of the high- k gate stack, indicating room for improvement by optimization of processing or by implementation of a suitable bulk-oxide defect passivation step.IEEE Transactions on Device and Materials Reliability 01/2013; 13(4):444-455. · 1.54 Impact Factor