LowPower Amplifier for Readout Interface of Semiconductor Scintillator
ABSTRACT We present the design of a readout system, comprising a charge sensitive amplifier and a pulse shaper, that directly interfaces a semiconductor scintillator. The designed amplifier quantifies optical response of a largearea epitaxial photodiode that registers luminescence produced by a scintillating semiconductor wafer when excited by ionizing radiation. The epitaxial photodiode is characterized by a capacitance of 50 pF and a dark current of 10 pA. The presented optimization procedure for the biasing and sizing the input transistor of the CSA directly relates the region of operation of the input transistor with the constraints on power, area and event rate of the readout system. Experimental results of the amplifier implemented in 0.5 μm CMOS technology, verify gain of 71 mV/fC, with the measured linearity of 1.3%. For the parameters of the photodiode, the measured equivalent noise charge (ENC) is 950 electrons with the measured time constant of the pulse shaper of 90 μs and the power consumption of 210 μW. The measured slope of the ENC dependence on the input capacitance is 18 e^{}/pF.

Conference Paper: Lownoise readout IC with integrated analogtodigital conversion for radiation detection system
[Show abstract] [Hide abstract]
ABSTRACT: A lownoise readout integrated circuit, comprising a charge sensitive amplifier, a pulse shaper with baseline holder, a peak detector and an A/D converter, is presented. The designed IC quantifies optical response of a largearea epitaxial photodiode integrated on a body of a semiconductor scintillator. The input transistor size and the time constant of the shaper are optimized to obtain a minimum equivalent noise charge(ENC) with the large input load capacitance. A timebased clockless A/D converter is implemented to minimize the interference of the digital part of the readout system on the lownoise chargesensitive amplifier. The simulated ENC of the readout system interfacing a 50 pF capacitance and a dark current of 10 pA that model the epitaxial photodiode is 172 electrons at 12 μs time constant of the pulse shaper with power consumption of CSA and shaper of 2.2 mW.Circuits and Systems (ISCAS), 2013 IEEE International Symposium on; 01/2013  SourceAvailable from: Serge Luryi
Article: LIST OF SCIENTIFIC PUBLICATIONS
Page 1
IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 58, NO. 4, AUGUST 2011 2129
LowPower Amplifier for Readout Interface of
Semiconductor Scintillator
Xiao Yun, Student Member, IEEE, Milutin Stanac ´evic ´, Member, IEEE, and Serge Luryi, Fellow, IEEE
Abstract—Wepresentthedesignofareadoutsystem,comprising
a charge sensitive amplifier and a pulse shaper, that directly inter
faces a semiconductor scintillator. The designed amplifier quanti
fies opticalresponseofa largeareaepitaxial photodiodethatregis
ters luminescence producedby a scintillatingsemiconductor wafer
when excited by ionizing radiation. The epitaxial photodiode is
characterized by a capacitance of 50 pF and a dark current of
10 pA. The presented optimization procedure for the biasing and
sizing the input transistor of the CSA directly relates the region
of operation of the input transistor with the constraints on power,
area and event rate of the readout system. Experimental results
of the amplifier implemented in 0.5
gain of 71 mV/fC, with the measured linearity of 1.3%. For the pa
rameters of the photodiode, the measured equivalent noise charge
(ENC)is950electronswiththemeasuredtimeconstantofthepulse
shaper of 90
? and the power consumption of 210
sured slope of the ENC dependence on the input capacitance is 18
? ??.
? CMOS technology, verify
?. The mea
Index Terms—Charged sensitive amplifier, pulse shaper, radia
tion detection, readout IC, scintillator.
I. INTRODUCTION
T
vices or materials has been an increasingly important national
security issue. Scintillating solidstate radiation detectors [1]
register ionizing radiation by converting the energy of the inci
dent radiation into light measured by a coupled photodetector.
Due to inherent nonproportionality response and the resulting
poor resolution of the dielectric scintillators [2], [3], the im
plementation of semiconductor scintillators could potentially
bring a significant leap in the energy resolution [4]. The chal
lenge in developing a semiconductor scintillator is how to make
the material transmit its own infrared luminescence. Two dif
ferent approaches have been proposed for the directgap semi
conductors, like InP and GaAs. In the first, the semiconductor
is heavily doped with the donor impurities, in order to intro
duce the Burstein shift between the emission and the absorp
tion spectra [5]. The second approach is based on the extremely
HE enhancement and deployment of radiological detec
tion capabilities to prevent the illicit use of nuclear de
Manuscript received November 29, 2010; revised March 07, 2011 and April
21, 2011; accepted May 07, 2011. Date of publication July 07, 2011; date of
current version August 17, 2011. This work was supported by the Domestic
Nuclear Detection Office (DNDO), Department of Homeland Security.
The authors are with the Department of Electrical and Computer Engi
neering, Stony Brook University, Stony Brook, NY 117942350 USA (email:
milutin@ece.sunysb.edu).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TNS.2011.2159311
Fig.1. (a)Illustrationofa3Dscintillatorarray.Eachunitcontainsthesemicon
ductor scintillator as radiation detector and readout ASIC. (b) Semiconductor
scintillator comprising a scintillator body and an integrated photodiode (top
plate) on its surface. Since the thickness of the photodiode is a small fraction of
the thickness of the scintillator body, we expect a negligible number of events
to be generated in the diode.
highradiativeefficiencyofhighquality directgapsemiconduc
tors. In highquality InP, a scintillation photon is not completely
lost in an act of interband absorption, since a newly created
minority carrier generates upon recombination a new scintil
lation photon in a random direction [4], [6]. Recent progress
towards realization of the InP scintillator is described in [7].
An important advantage of the semiconductor scintillator is the
ability to integrate an epitaxial photodiode [7] on the scintil
lator body, ensuring nearly perfect registration of the scintilla
tion photons. Based on the Compton telescope technique [8],
a threedimensional array [4] of semiconductor scintillators (il
lustratedinFig.1)providesanaccuratespectroscopicresolution
forisotopediscriminationandsimultaneouslyanaccuratedeter
mination of the direction to the source. To measure the optical
response of the epitaxial photodiode, an application specific in
tegrated circuit (ASIC) has to be integrated with the detector.
00189499/$26.00 © 2011 IEEE
Page 2
2130 IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 58, NO. 4, AUGUST 2011
There have been numerous examples in the literature of the
readout ASICs [9]–[12] for radiation detection, where both cir
cuit implementation and integration strongly depend on the de
tector and the application. In the proposed semiconductor scin
tillator array, the size of the single pixel epitaxial photodiode is
1 mm
1 mm. A large area of the photodiode gives rise to a
large capacitance, measured at 50 pF [7]. The large diode ca
pacitance leads to a higher noise figure and a potential insta
bility in the amplifier design. Despite the large diode area, the
reversebiasleakage current is rather low, on the orderof 10 pA.
The main challenge in the design of the readout ASIC is to min
imize the input noise so as to achieve the high sensitivity and
prevent false alarms. As the proposed 3D integration calls for a
considerable volume with a large number of pixels, strict con
straints are imposed on the power consumption and size of the
readout ASIC. We envision a
1
in volume, with each array element directly interfaced
to a thinned single channel readout ASIC. The purpose of the
3D array is not only to enhance the interaction efficiency with
incidentgammaphotons,butmostimportantlytoresolvetheen
ergy and the location of the first three interactions, as required
for Compton analysis. Careful design of the readout system, es
pecially the charge sensitive amplifier (CSA), is required to op
timize noise given the power and area. Previously reported opti
mization procedures [13]–[15] for sizing the input transistor of
the CSA had focused on achieving an unconstrained noise min
imum and therefore were primarily interested in accurate noise
modeling. Here we shall derive an optimization procedure that
directly relates the region of operation of the input transistor to
different constraints on the readout system. To do this we shall
use tractable models that describe the transistor’s operation and
noise. The optimization procedure will be applied to the design
of the readout circuit that will be integrated with the described
scintillatorphotodiode unit into a 3D array for radiation detec
tion.
array,
II. INPUT TRANSISTOR OPTIMIZATION
The readout system, comprising a charge sensitive amplifier
and a pulse shaper, is adopted to estimate the theoretical noise
floor in the detection of an ionizing radiation event. The op
timization of the input MOS transistor of the CSA is derived
under the assumption that the total noise of the readout system
isdominatedbythecontributionoftheinputtransistor.Thesen
sitivityofthereadoutsystemisexpressedthroughtheequivalent
noise charge (ENC) [17]. The ENC has three main components:
(1) the white and (2) the flicker
the input MOS transistor, and (3) the white parallel noise, due
to the detector leakage current and the feedback network [13]:
series noise, originated in
(1)
(2)
(3)
where
and order of the pulse shaper;
thatdependsontheoperationregionofthetransistor;
, and are constants that depend on the type
is the thermal noise coefficient
and
are respectively the transconductance and the gate capacitance
of the input transistor;
is the load capacitance at the CSA
input,which is thesum of the detectorcapacitance
back capacitance
and possibly other parasitic capacitances
resulting from interconnects;
is the time constant of the pulse
shaper;
is the detector leakage current and
ficient associated with the flicker noise of the input transistor.
As the transconductance and noise parameters of the tran
sistor depend on the region of operation, the optimization pro
cedure for sizing and biasing the input transistor is formulated
separately for the strong and the weakinversion regions of
operation. The transconductance of a transistor biased in the
stronginversion region can be approximated as:
, the feed
is the coef
(4)
and in the weakinversion region as:
(5)
where
where
ature,
per unit area, ,
the width and the length of the input transistor.
The flicker noise of MOS transistors may have two different
origins [14], [16]. The
model assumes that the flicker noise
in the drain current results from the fluctuation in the number of
charge carriers. On the other hand, the
theflickernoiseisgeneratedbythefluctuationinthemobilityof
charge carriers. In our optimization procedure it is assumed that
the input transistor is PMOS. In the 0.5
a PMOS transistor has two orders of magnitude lower flicker
noise than a NMOS transistor. Studies have shown that PMOS
transistors might follow the
inversion and the
model when biased in strong inversion.
Therefore, the flicker noise voltage spectral density
expressed as:
is the subthreshold slope coefficient,
istheBoltzmannconstantand
is thecarriermobility,
andare respectively the biasing current,
,
istheabsolutetemper
is thegate oxide capacitance
model assumes that
CMOS technology,
model when biased in weak
can be
(6)
(7)
where
density at the quasi Fermi level per unit volume, and
tunneling parameter of the traps. The
noise increases with the square root of the biasing current ,
while the
model predicts that the noise is independent of .
is the Hooge constant,is the oxide/interface trap
is the
model predicts that the
A. Input Transistor Biased in Strong Inversion
Thederivationoftheoptimalsizingoftheinputtransistorthat
operates in the stronginversion region is presented in [14]. The
total ENC is expressed in terms of three design variables: the
Page 3
YUN et al.: LOWPOWER AMPLIFIER FOR READOUT INTERFACE OF SEMICONDUCTOR SCINTILLATOR 2131
Fig. 2. Minimum ENC as a function of fixed biasing current, with no con
straintson? and? .Theinputtransistorisassumedtobeeitherinthestrongin
version or in the weakinversion regime.
biasing current , the gate capacitance of the input transistor
and the shaping time constant
(8)
where
, and are constants:
(9)
For the proposed detector, with a capacitance of 50 pF and
a leakage current of 10 pA, the unconstrained optimization of
(8) in 0.5
CMOS technology leads to a minimum ENC of
83
at a biasing current of 22 mA, which is significantly over
the power consumption limit of the readout system. The length
of the input transistor is 1.2
minimum feature length of the fabrication process (0.6
improve the gain of the highgain amplifier in the CSA. The
optimal width of the input transistor is 33.6 mm and the optimal
shaping time constant is 11
.
1) Constrained Optimization: The constraints on the opti
mization of the ENC originate from the limits on the three de
sign variables; the rate of radiation events gives the upper limit
of , the power budget of the readout system limits the biasing
current, and the chip area limits the capacitance
refer to design variables optimized under constraints as the sub
optimum parameters.
Fig. 2 shows the minimum achievable ENC for the case of
a fixed biasing current [14] with no constraints on
assuming that the input transistor operates in strong inversion.
When the biasing current limit is higher than the optimal cur
rent
obtained in the unconstrained optimization, the sub
optimum capacitive ratio tends toward
noise becomesdominant;when thebiasing currentis lowerthan
. It has been chosen above the
) to
. We shall
and,
as the
, the suboptimum capacitive ratio moves to
as the thermal noise becomes dominant. If the biasing current is
further lowered to a point that even
the input transistor in the stronginversion regime, the subop
timum is reached at
If the shaping time constant is limited by the event rate, the
suboptimum biasing current is higher than
timum capacitive ratio moves toward
shorter shaping time constant results in the larger thermal noise
contribution.
cannot keep
.
. The subop
, since a
B. Input Transistor Biased in Weak Inversion
The ENC for the case of the input transistor operating in
the weakinversion regime can be obtained by inserting the
transconductance (5) into (1) and the
flicker noise into (2)
model (6) for the
(10)
(11)
The total ENC can be expressed as:
(12)
where
Thereisanoptimumvaluefor ,as
while increases with . For a given
decreases continuously as the biasing current
andare fixed, the minimum thermal noise is achieved at the
lowest
; the minimum for the flicker noise is achieved for
.
1) Unconstrained Optimization: In order to have the input
transistor biased in the weakinversion regime, the following
condition has to be satisfied [14]:
, and are constants.
decreaseswith
,
is increased. If
(13)
where
(14)
This leads to an upper limit on the biasing current
(15)
Therefore, the optimum
keeps the input transistor in the weakinversion regime:
is chosen as the largest current that
(16)
Page 4
2132 IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 58, NO. 4, AUGUST 2011
where
(17)
The optimum
tives of (12) with zero, which gives the unconstrained weakin
version optima in the form:
and can be found by equating partial deriva
(18)
When the above optima are feasible, the absolute minimum
ENC in the weakinversion regime is:
(19)
For our specific sensor, the unconstrained optimization leads
to a minimum ENC of 348
at the biasing current of 44
The input transistor width is 33 mm and the shaping time con
stant is 124
. Therefore, the power consumption can be re
duced by more than two orders of magnitude, while the penalty
in the ENC is an increase by a factor of four.
2) ConstrainedOptimization: Hereweconsiderthesituation
when one of the three design variables is constrained. When the
biasing current
is fixed, the suboptimum
as
.
can be calculated
(20)
After inserting (20) into (12), the suboptimum ENC becomes a
function of
, viz.
(21)
The first term in (21) is minimized by the smallest value of
that still keeps the transistor biased in weak inversion. The
second term in (21) is minimized by
dependence of
as a function of the fixed biasing
current, with
and the value of
imize (21).
If
is limited due to the area constraint, the optimum bi
asing current has to be chosen as the largest value to keep the
transistorintheweakinversionregime,or
optimum
can still be calculated as
. Fig. 2 shows the
selected to min
.The
(22)
Fig. 3. Minimum ENC for a fixed capacitive ratio of ? and ? , with no con
straints on ? and ?, when the input transistor is in the weakinversion regime.
Fig. 4. Minimum ENC as a function of a fixed time constant of the shaper
scaled by the optimal time constant when the input transistor is in the weakin
version regime.
which gives the suboptimum ENC
(23)
Fig. 3 shows the minimum ENC for different capacitive ratios
of
and. We can notice that the minimum value of ENC
worsens by 10% when the input transistor size is at 30% of its
optimum value.
If the shaping time constant is fixed, due to the rate of ion
izing radiation events, the same optimization procedure results
in
,
now calculated as
. The suboptimum ENC is
(24)
Fig. 4 shows the minimum ENC as a function of a fixed time
constant.
C. Comparison of Weak Inversion and Strong Inversion
When the absolute minimum noise is desired, the transistor
must be in the stronginversion regime. However, in circum
Page 5
YUN et al.: LOWPOWER AMPLIFIER FOR READOUT INTERFACE OF SEMICONDUCTOR SCINTILLATOR2133
stances where the biasing current of the input transistor is lim
ited due to the power constraints, the optimal region of the tran
sistor operation depends on the power constraint. The optimum
point also varies with the different sensor parameters and the
noise requirement.
In the design of the proposed readout system we have rela
tively flexible choices over the time constant and the input tran
sistor size. However, the power consumption is constrained. For
this case, with fixed biasing current and no constraints on
, we compare the minimum achievable ENC for the cases of
theinputtransistorbiasedinthestronginversionregimeandthe
weakinversion regime, see Fig. 2. The biasing currents are lim
ited to 100
, which is reasonable for most readout systems.
In the stronginversion regime, the ENC monotonically de
creases as the current increases. For a small biasing current,
the gate capacitance of the input transistor cannot be made suf
ficiently large to match
. Therefore, the minimum ENC is
achieved when
is the largest value that keeps the input tran
sistor in strong inversion. In the weakinversion regime, a min
imum value of ENC is achieved at
current equals the largest value that keeps the input transistor
in weak inversion. From Fig. 2, we can conclude that when the
biasing current is limited to 100
is preferred over the stronginversion regime; when the biasing
current is higher, the stronginversion regime becomes the pre
ferredregionofoperation.Themoderateinversionregionofop
eration of the input transistor is omitted in the comparison due
to the lack of tractable noise models.
and
and the biasing
, the weakinversion regime
III. AMPLIFIER IMPLEMENTATION
The detailed circuit implementation of the amplifier, com
prising a CSA and a pulse shaper, is outlined in this Section.
The optimization technique proposed in SectionII is appliedfor
sizing the input transistor.
A. Charge Sensitive Amplifier
Conventional architecture of the CSA with a highgain am
plifier and a small feedback capacitor for the input charge in
tegration is implemented as the first stage of amplification. In
order to increase the overall gain provided by the input ampli
fication stage, a twostage cascaded chargesensitive amplifier
is implemented, as shown in Fig. 5. To ensure high linearity of
the firststage of the CSA, a polezero compensation network
is formed by a parallel connection of
back network formed by capacitor
second CSA stage increases the overall gain by a factor of
leading to the total gain of
plementation. The value of the DC voltage at the input of both
highgain amplifiers is designed to be the same, so as to pro
vide equal biasing conditions for transistors
which is necessary for the high linearity of the CSA. The choice
of feedback capacitors is influenced by the high detector capac
itance; the feedback capacitors are set at
Fig. 6 shows the foldedcascode implementation of the high
gain amplifier in the first stage of CSA. The PMOS input tran
sistor is chosen over NMOS due to its lower flicker noise. The
widthoftheinputtransistoris16.2mmandthegatelengthis1.2
replicas of the feed
and transistor. The
,
in the proposed im
and,
.
Fig. 5. Cascaded CSA implementation.
Fig. 6. Foldedcascode with cascaded source follower as a highgain amplifier
in the CSA.
. We found by simulation that the DC gain of the foldedcas
code amplifier is 94 dB. The feedback transistor
in the subthreshold regime due to the low (10 pA) leakage cur
rent of the detector.
1) Noise Contributions From Other Transistors: The addi
tional noise contributions from
imated as:
operates
, and can be approx
(25)
where
the gates of
namic resistance seen at the source node of
ferred voltage noise from
ductance of
. Because
rent, and NMOS transistors have at least one order of magni
tude higher flicker noise coefficient than PMOS, the noise con
tribution from
cannot be neglected. To reduce the thermal
noise from
has to be small, which leads to a higher
voltage drop for the fixed biasing current. To reduce the flicker
noise from
, the length of the transistor is increased [14].
Noise from
can be neglected due to the large resistance
The optimization procedure presented in Section II is adjusted
to take into account the additional noise sources from (25).
2) Stability Analysis: The large input transistor makes the
nondominant pole located at the folding node close to the dom
inant pole located at the output of the foldedcascode amplifier;
, and
,
are the inputreferred noise sources at
and , respectively, andis the dy
. The inputre
and
and
is scaled by the transcon
have similar biasing cur
.
Page 6
2134 IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 58, NO. 4, AUGUST 2011
Fig.7. Opencircuitschematicofthefirststagevoltageamplifierafterbreaking
the loop.
thus, the stability of the CSA requires careful examination [18].
Assuming that the source follower is an ideal buffer and that the
reset MOS transistor
has a very large equivalent resistance
, the openloop circuit can be modeled as shown in Fig. 7,
where
total capacitance at the folding node;
code of
and; is the capacitance at the output of the
folded cascode amplifier and
output. Thus, the loop gain can be derived as:
is the
is the resistance of cas
is the capacitance at the CSA
(26)
where zero and poles are located at
(27)
We attribute pole
capacitive load, while
with the voltage amplifier. The feedforward zero comes from
the
feedback network. The unitygain frequency
approximated as:
to the feedback capacitor and the input
and are the two poles associated
can be
(28)
Sincethefirstpoleandzeroare atrelativelylowfrequency,their
phase contribution can be approximately canceled. Therefore,
the first nondominant pole
mines the phase margin of the loop. It is reasonable to assume
that the CSA’s nondominant pole is fixed, thus it is desirable to
place
far away from. A smaller
stable; however a large amplifier gain is required due to a high
ratio. Thus, adding a compensation capacitive load to
is the only feasible option. In our design, the value of
is 2 pF and the achieved phase margin is over 70 . Though the
added compensation capacitor slows the circuit’s step response
to over 3
, a time constant of 100
means that the overall readout system is not affected.
is critical and ultimately deter
makes the CSA more
of the following shaper
Fig. 8. (a) Implementation of the pulse shaper. (b) Schematic of ICON cell.
Since the input capacitance of the second highgain amplifier
in Fig. 5 is significantly smaller than that for the first amplifier,
thesecondamplifierisdesignedasafivetimesscaleddownver
sion of the first amplifier. The additional compensation capac
itor is not required for the second amplifier.
B. Pulse Shaper
The calculated optimum shaping time constant for the pro
posed amplifier is fairly large, 100
high capacitance and the low leakage current of the detector.
This time constant requires that there be no more than 30,000
photons/sec incident on a pixel. In order to achieve such a long
shaping time with the constraints of area and power, we have
chosen a filter based on ICON RC cell [19] that provides both
the lowarea and the lowpower shaper implementation. The
schematic of the two stage pulse shaper is shown in Fig. 8(a).
The ICON cell, shown in Fig. 8(b), makes the equivalent re
sistance
times higher than the integrated physical resistance
due to the ratio of
in the current mirrors. The amplifiers in
the shaper are a scaled down version of the highgain amplifier
in the CSA, thus ensuring the same amplifier DC level.
, as a consequence of the
IV. RESULTS
The proposed readout system was implemented in 0.5
CMOS technology with the measured flickernoise parameter
of the PMOS transistor equal to
themicrographofthesinglechannelofthechiphighlightingthe
functionalblocksdescribedinSectionsIIIAandIIIB.Thesize
of a single channel is 1.1 mm
of the implemented preamplifier was conducted at 3.3 V supply
voltage.
The fabricated preamplifier is characterized without a sensor.
The chiponboard technique was employed to wirebond the
. Fig. 9 shows
0.4 mm. The characterization
Page 7
YUN et al.: LOWPOWER AMPLIFIER FOR READOUT INTERFACE OF SEMICONDUCTOR SCINTILLATOR2135
Fig. 9. Microphotoofthe implementedsinglepreamplifier channel,containing
CSA and pulse shaper, in 0.5?? CMOS technology.
Fig. 10. Measured output voltage of the CSA for different values of the input
charge.
die directly on the printed circuit board. A 1 pF capacitor that
is connected externally to the input of the CSA enables a con
trolled charge injection into the readout circuitry, as the current
pulse at the input is generated by applying a known voltage
step signal to the capacitor. A dc current is injected into the
input node of the CSA through a 1
through an onboard DAC. To model sensors capacitance in the
characterization of the noise performance of the preamplifier,
different external capacitors were used at the input node.
Fig. 10 shows the response of the CSA for different voltage
steps that correspond to the total input injected negative charge
of either 5000 or 10,000 or 20,000 electrons. Due to the small
leakage current of the detector and biasing of the feedback tran
sistor in the subthreshold regime, the decay time of the CSA is
on the order of milliseconds. Fig. 11 shows the measured output
signalafterthepulseshaper.Theshapingtimeconstantis90
The measured charge gain is 71 mV/fC. The measured linearity
of the CSA is 0.4%, while the measured linearity of the ampli
fier, consisting of the CSA and the pulse shaper, is 1.3%. A plot
of the output voltage of the amplifier as function of the input
charge is shown in Fig. 12.
The measure of the chip sensitivity is ENC. The measured
r.m.s. ENC (for the detector capacitance fixed at 50 pF and
the leakage current fixed at 10 pA) is 950 electrons, a higher
value than predicted. The minimum detectable signal of 3000
electrons corresponds to gamma energy resolution of 15 keV.
Fig.13showsthemeasuredENCfordifferentvaluesoftheinput
capacitance andthemeasuredslope is 18
power consumption of a single channel is 210
mance of the implemented amplifier is matched to the required
minimum detectable signal and the input range of the proposed
radiation detector.
resistor and is controlled
.
.Themeasured
. The perfor
Fig. 11. Measured output voltage of the pulse shaper for different values of the
input charge.
Fig. 12. Measured output voltage of the amplifier as a function of the input
charge.
Fig. 13. Measured ENC as a function of the input capacitance.
V. CONCLUSION
We presented the design and the implementation of a low
noise, lowpower amplifier to register the semiconductor scin
tillator signal excited by ionizing radiation. To increase the sen
sitivity of the readout circuitry under the area, power and event
rateconstraints,wehavedevisedanoveloptimizationtechnique
and applied it to the design of the CSA. The integration of the
proposed readout amplifier and semiconductor scintillator in a
3D array will provide both isotope discrimination and angular
resolution in various homeland security applications.
Page 8
2136 IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 58, NO. 4, AUGUST 2011
ACKNOWLEDGMENT
The authors are grateful to Gianluigi De Geronimo
(Brookhaven National Lab) for useful discussions and re
view of the paper.
REFERENCES
[1] G. F. Knoll, Radiation Detection and Measurement, 3rd ed.
York: Wiley, 2000.
[2] A. N. Vasilev, “From luminescence nonlinearity to scintillation non
proportionality,” IEEE Trans. Nucl. Sci., vol. 55, no. 3, pp. 1054–1061,
Jun. 2008.
[3] S. A. Payne, N. J. Cherepy, G. Hull, J. D. Valentine, W. W. Moses, and
W.S. Choong, “Nonproportionality of scintillator detectors: Theory
andexperiment,”IEEETrans.Nucl.Sci.,vol.56,no.4,pp.2506–2512,
Aug. 2009.
[4] S. Luryi and A. Subashiev, Semiconductor Scintillator for 3Dimen
sional Array of Radiation Detectors.
2010, pp. 331–346.
[5] A. Kastalsky, S. Luryi, and B. Spivak, “Semiconductor highenergy
radiation scintillation detector,” Nucl. Instrum. Methods Phys. Res. A,
vol. 565, pp. 650–656, 2006.
[6] S. Luryi and A. Subashiev, “Semiconductor scintillator based on
photon recycling,” Nucl. Instrum. Methods Phys. Res. A, 2011,
10.1016/j.nima.2011.01.136.
[7] S. Luryi, A. Kastalsky, M. Gouzman, N. Lifshitz, O. Semyonov, M.
Stanacevic, A. Subashiev, V. Kuzminsky, W. Cheng, V. Smagin, Z.
Chen, J. H. Abeles, and W. K. Chan, “Epitaxial InGaAsP/InP pho
todiode for registration of InP scintillation,” Nucl. Instrum. Methods
Phys. Res. A, vol. 622, pp. 113–119, 2010.
[8] E. Aprile, A. Bolotnikov, D. Chen, and R. Mukherjee, “A Monte Carlo
analysis of the liquid xenon TPC as gammaray telescope,” Nucl. In
strum. Methods Phys. Res. A, vol. 327, pp. 216–221, 1993.
New
New York: Wiley Interscience,
[9] G. De Geronimo, J. Fried, E. Frost, B. F. Phlips, E. Vernon, and E. A.
Wulf, “Frontend ASIC for a silicon compton telescope,” IEEE Trans.
Nucl. Sci., vol. 55, no. 4, pp. 2323–2328, Aug. 2008.
[10] S. Caccia, G. Bertuccio, D. Maiocchi, P. Malcovati, N. Ratti, and D.
Martin, “A mixedsignal spectroscopicgrade and highfunctionality
CMOSreadoutcellforsemiconductor??? raypixeldetectors,”IEEE
Trans. Nucl. Sci., vol. 55, no. 5, pp. 2721–2726, Oct. 2008.
[11] B. Krieger, K. Ewell, B. A. Ludewigt, M. R. Maier, D. Markovic, O.
Milgrome,andY.J.Wang,“An8?8pixelICforXrayspectroscopy,”
IEEE Trans. Nucl. Sci., vol. 48, no. 3, pp. 493–498, Jun. 2001.
[12] K. T. Z. Oo, E. Mandelli, and W. W. Moses, “A highspeed lownoise
16channel CSA with automatic leakage compensation in 0.35 ??
CMOSprocess for APDbased PET detectors,”IEEE Trans. Nucl. Sci.,
vol. 54, no. 3, pp. 444–453, Jun. 2007.
[13] G. De Geronimo and P. O’Connor, “MOSFET optimization in deep
submicron technology for charge amplifiers,” IEEE Trans. Nucl. Sci.,
vol. 52, no. 6, pp. 3223–3232, Dec. 2005.
[14] G. Bertuccio and S. Caccia, “Noise minimization of MOSFET input
charge amplifiers based on ?? and ?? 1/f models,” IEEE Trans. Nucl.
Sci., vol. 56, no. 3, pp. 1511–1520, Jun. 2009.
[15] L. Ratti, M. Manghisoni, V. Re, and G. Traversi, “Design optimization
ofchargepreamplifierswithCMOSprocessesinthe100nmgatelength
regime,”IEEETrans.Nucl.Sci.,vol.56,no.1,pp.235–242,Feb.2009.
[16] M. Valenza, A. Hoffmann, D. Sodini, A. Laigle, F. Martinez, and D.
Rigaud, “Overview of the impact of downscaling technology on 1/f
noise in pMOSFETs to 90 nm,” IEE Proc.–Circuits, Devices Syst.,
vol. 151, no. 2, pp. 102–110, 2004.
[17] W.M.C.SansenandZ.Y.Chang,“Limitsoflownoiseperformanceof
detectorreadoutfrontendsinCMOStechnology,”IEEETrans.Circuits
Syst., vol. 37, no. 11, pp. 1375–1382, 1990.
[18] X. Yun, S. Luryi, and M. Stanacevic,“Lowpowercharge sensitive am
plifierforsemiconductorscintillator,”inProc.IEEEInt.Symp.Circuits
and Systems, Paris, France, 2010.
[19] C. Fiorini and M. Porro, “Integrated RC cell for timeinvariant shaping
amplifiers,” IEEE Trans. Nucl. Sci., vol. 51, no. 5, pp. 1953–1960, Oct.
2004.
View other sources
Hide other sources
 Available from Serge Luryi · Jun 6, 2014
 Available from sunysb.edu