IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 58, NO. 4, AUGUST 20112129
Low-Power Amplifier for Readout Interface of
Xiao Yun, Student Member, IEEE, Milutin Stanac ´evic ´, Member, IEEE, and Serge Luryi, Fellow, IEEE
a charge sensitive amplifier and a pulse shaper, that directly inter-
faces a semiconductor scintillator. The designed amplifier quanti-
fies opticalresponseofa large-areaepitaxial photodiodethatregis-
ters luminescence producedby a scintillatingsemiconductor wafer
when excited by ionizing radiation. The epitaxial photodiode is
characterized by a capacitance of 50 pF and a dark current of
10 pA. The presented optimization procedure for the biasing and
sizing the input transistor of the CSA directly relates the region
of operation of the input transistor with the constraints on power,
area and event rate of the readout system. Experimental results
of the amplifier implemented in 0.5
gain of 71 mV/fC, with the measured linearity of 1.3%. For the pa-
rameters of the photodiode, the measured equivalent noise charge
shaper of 90
? and the power consumption of 210
sured slope of the ENC dependence on the input capacitance is 18
? CMOS technology, verify
?. The mea-
Index Terms—Charged sensitive amplifier, pulse shaper, radia-
tion detection, readout IC, scintillator.
vices or materials has been an increasingly important national
security issue. Scintillating solid-state radiation detectors 
register ionizing radiation by converting the energy of the inci-
dent radiation into light measured by a coupled photo-detector.
Due to inherent non-proportionality response and the resulting
poor resolution of the dielectric scintillators , , the im-
plementation of semiconductor scintillators could potentially
bring a significant leap in the energy resolution . The chal-
lenge in developing a semiconductor scintillator is how to make
the material transmit its own infrared luminescence. Two dif-
ferent approaches have been proposed for the direct-gap semi-
conductors, like InP and GaAs. In the first, the semiconductor
is heavily doped with the donor impurities, in order to intro-
duce the Burstein shift between the emission and the absorp-
tion spectra . The second approach is based on the extremely
HE enhancement and deployment of radiological detec-
tion capabilities to prevent the illicit use of nuclear de-
Manuscript received November 29, 2010; revised March 07, 2011 and April
21, 2011; accepted May 07, 2011. Date of publication July 07, 2011; date of
current version August 17, 2011. This work was supported by the Domestic
Nuclear Detection Office (DNDO), Department of Homeland Security.
The authors are with the Department of Electrical and Computer Engi-
neering, Stony Brook University, Stony Brook, NY 11794-2350 USA (e-mail:
Color versions of one or more of the figures in this paper are available online
Digital Object Identifier 10.1109/TNS.2011.2159311
ductor scintillator as radiation detector and readout ASIC. (b) Semiconductor
scintillator comprising a scintillator body and an integrated photodiode (top
plate) on its surface. Since the thickness of the photodiode is a small fraction of
the thickness of the scintillator body, we expect a negligible number of events
to be generated in the diode.
tors. In high-quality InP, a scintillation photon is not completely
lost in an act of interband absorption, since a newly created
minority carrier generates upon recombination a new scintil-
lation photon in a random direction , . Recent progress
towards realization of the InP scintillator is described in .
An important advantage of the semiconductor scintillator is the
ability to integrate an epitaxial photodiode  on the scintil-
lator body, ensuring nearly perfect registration of the scintilla-
tion photons. Based on the Compton telescope technique ,
a three-dimensional array  of semiconductor scintillators (il-
mination of the direction to the source. To measure the optical
response of the epitaxial photodiode, an application specific in-
tegrated circuit (ASIC) has to be integrated with the detector.
0018-9499/$26.00 © 2011 IEEE
2130 IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 58, NO. 4, AUGUST 2011
There have been numerous examples in the literature of the
readout ASICs – for radiation detection, where both cir-
cuit implementation and integration strongly depend on the de-
tector and the application. In the proposed semiconductor scin-
tillator array, the size of the single pixel epitaxial photodiode is
1 mm. A large area of the photodiode gives rise to a
large capacitance, measured at 50 pF . The large diode ca-
pacitance leads to a higher noise figure and a potential insta-
bility in the amplifier design. Despite the large diode area, the
reverse-biasleakage current is rather low, on the orderof 10 pA.
The main challenge in the design of the readout ASIC is to min-
imize the input noise so as to achieve the high sensitivity and
prevent false alarms. As the proposed 3D integration calls for a
considerable volume with a large number of pixels, strict con-
straints are imposed on the power consumption and size of the
readout ASIC. We envision a
in volume, with each array element directly interfaced
to a thinned single channel readout ASIC. The purpose of the
3D array is not only to enhance the interaction efficiency with
ergy and the location of the first three interactions, as required
for Compton analysis. Careful design of the readout system, es-
pecially the charge sensitive amplifier (CSA), is required to op-
timize noise given the power and area. Previously reported opti-
mization procedures – for sizing the input transistor of
the CSA had focused on achieving an unconstrained noise min-
imum and therefore were primarily interested in accurate noise
modeling. Here we shall derive an optimization procedure that
directly relates the region of operation of the input transistor to
different constraints on the readout system. To do this we shall
use tractable models that describe the transistor’s operation and
noise. The optimization procedure will be applied to the design
of the readout circuit that will be integrated with the described
scintillator-photodiode unit into a 3D array for radiation detec-
II. INPUT TRANSISTOR OPTIMIZATION
The readout system, comprising a charge sensitive amplifier
and a pulse shaper, is adopted to estimate the theoretical noise
floor in the detection of an ionizing radiation event. The op-
timization of the input MOS transistor of the CSA is derived
under the assumption that the total noise of the readout system
noise charge (ENC) . The ENC has three main components:
(1) the white and (2) the flicker
the input MOS transistor, and (3) the white parallel noise, due
to the detector leakage current and the feedback network :
series noise, originated in
and order of the pulse shaper;
, and are constants that depend on the type
is the thermal noise coefficient
are respectively the transconductance and the gate capacitance
of the input transistor;
is the load capacitance at the CSA
input,which is thesum of the detectorcapacitance
and possibly other parasitic capacitances
resulting from interconnects;
is the time constant of the pulse
is the detector leakage current and
ficient associated with the flicker noise of the input transistor.
As the transconductance and noise parameters of the tran-
sistor depend on the region of operation, the optimization pro-
cedure for sizing and biasing the input transistor is formulated
separately for the strong- and the weak-inversion regions of
operation. The transconductance of a transistor biased in the
strong-inversion region can be approximated as:
, the feed-
is the coef-
and in the weak-inversion region as:
per unit area, ,
the width and the length of the input transistor.
The flicker noise of MOS transistors may have two different
origins , . The
model assumes that the flicker noise
in the drain current results from the fluctuation in the number of
charge carriers. On the other hand, the
charge carriers. In our optimization procedure it is assumed that
the input transistor is PMOS. In the 0.5
a PMOS transistor has two orders of magnitude lower flicker
noise than a NMOS transistor. Studies have shown that PMOS
transistors might follow the
inversion and the
model when biased in strong inversion.
Therefore, the flicker noise voltage spectral density
is the subthreshold slope coefficient,
andare respectively the biasing current,
is thegate oxide capacitance
model assumes that
model when biased in weak
density at the quasi Fermi level per unit volume, and
tunneling parameter of the traps. The
noise increases with the square root of the biasing current ,
model predicts that the noise is independent of .
is the Hooge constant,is the oxide/interface trap
model predicts that the
A. Input Transistor Biased in Strong Inversion
operates in the strong-inversion region is presented in . The
total ENC is expressed in terms of three design variables: the
YUN et al.: LOW-POWER AMPLIFIER FOR READOUT INTERFACE OF SEMICONDUCTOR SCINTILLATOR 2131
Fig. 2. Minimum ENC as a function of fixed biasing current, with no con-
straintson? and? .Theinputtransistorisassumedtobeeitherinthestrong-in-
version or in the weak-inversion regime.
biasing current , the gate capacitance of the input transistor
and the shaping time constant
, and are constants:
For the proposed detector, with a capacitance of 50 pF and
a leakage current of 10 pA, the unconstrained optimization of
(8) in 0.5
CMOS technology leads to a minimum ENC of
at a biasing current of 22 mA, which is significantly over
the power consumption limit of the readout system. The length
of the input transistor is 1.2
minimum feature length of the fabrication process (0.6
improve the gain of the high-gain amplifier in the CSA. The
optimal width of the input transistor is 33.6 mm and the optimal
shaping time constant is 11
1) Constrained Optimization: The constraints on the opti-
mization of the ENC originate from the limits on the three de-
sign variables; the rate of radiation events gives the upper limit
of , the power budget of the readout system limits the biasing
current, and the chip area limits the capacitance
refer to design variables optimized under constraints as the sub-
Fig. 2 shows the minimum achievable ENC for the case of
a fixed biasing current  with no constraints on
assuming that the input transistor operates in strong inversion.
When the biasing current limit is higher than the optimal cur-
obtained in the unconstrained optimization, the sub-
optimum capacitive ratio tends toward
noise becomesdominant;when thebiasing currentis lowerthan
. It has been chosen above the
. We shall
, the suboptimum capacitive ratio moves to
as the thermal noise becomes dominant. If the biasing current is
further lowered to a point that even
the input transistor in the strong-inversion regime, the subop-
timum is reached at
If the shaping time constant is limited by the event rate, the
suboptimum biasing current is higher than
timum capacitive ratio moves toward
shorter shaping time constant results in the larger thermal noise
. The subop-
, since a
B. Input Transistor Biased in Weak Inversion
The ENC for the case of the input transistor operating in
the weak-inversion regime can be obtained by inserting the
transconductance (5) into (1) and the
flicker noise into (2)
model (6) for the
The total ENC can be expressed as:
while increases with . For a given
decreases continuously as the biasing current
and are fixed, the minimum thermal noise is achieved at the
; the minimum for the flicker noise is achieved for
1) Unconstrained Optimization: In order to have the input
transistor biased in the weak-inversion regime, the following
condition has to be satisfied :
, andare constants.
is increased. If
This leads to an upper limit on the biasing current
Therefore, the optimum
keeps the input transistor in the weak-inversion regime:
is chosen as the largest current that
2132 IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 58, NO. 4, AUGUST 2011
tives of (12) with zero, which gives the unconstrained weak-in-
version optima in the form:
and can be found by equating partial deriva-
When the above optima are feasible, the absolute minimum
ENC in the weak-inversion regime is:
For our specific sensor, the unconstrained optimization leads
to a minimum ENC of 348
at the biasing current of 44
The input transistor width is 33 mm and the shaping time con-
stant is 124
. Therefore, the power consumption can be re-
duced by more than two orders of magnitude, while the penalty
in the ENC is an increase by a factor of four.
2) ConstrainedOptimization: Hereweconsiderthesituation
when one of the three design variables is constrained. When the
is fixed, the suboptimum
can be calculated
After inserting (20) into (12), the suboptimum ENC becomes a
The first term in (21) is minimized by the smallest value of
that still keeps the transistor biased in weak inversion. The
second term in (21) is minimized by
as a function of the fixed biasing
and the value of
is limited due to the area constraint, the optimum bi-
asing current has to be chosen as the largest value to keep the
can still be calculated as
. Fig. 2 shows the
selected to min-
Fig. 3. Minimum ENC for a fixed capacitive ratio of ? and ? , with no con-
straints on ? and ?, when the input transistor is in the weak-inversion regime.
Fig. 4. Minimum ENC as a function of a fixed time constant of the shaper
scaled by the optimal time constant when the input transistor is in the weakin-
which gives the suboptimum ENC
Fig. 3 shows the minimum ENC for different capacitive ratios
and . We can notice that the minimum value of ENC
worsens by 10% when the input transistor size is at 30% of its
If the shaping time constant is fixed, due to the rate of ion-
izing radiation events, the same optimization procedure results
now calculated as
. The suboptimum ENC is
Fig. 4 shows the minimum ENC as a function of a fixed time
C. Comparison of Weak Inversion and Strong Inversion
When the absolute minimum noise is desired, the transistor
must be in the strong-inversion regime. However, in circum-
YUN et al.: LOW-POWER AMPLIFIER FOR READOUT INTERFACE OF SEMICONDUCTOR SCINTILLATOR2133
stances where the biasing current of the input transistor is lim-
ited due to the power constraints, the optimal region of the tran-
sistor operation depends on the power constraint. The optimum
point also varies with the different sensor parameters and the
In the design of the proposed readout system we have rela-
tively flexible choices over the time constant and the input tran-
sistor size. However, the power consumption is constrained. For
this case, with fixed biasing current and no constraints on
, we compare the minimum achievable ENC for the cases of
weak-inversion regime, see Fig. 2. The biasing currents are lim-
ited to 100
, which is reasonable for most readout systems.
In the strong-inversion regime, the ENC monotonically de-
creases as the current increases. For a small biasing current,
the gate capacitance of the input transistor cannot be made suf-
ficiently large to match
. Therefore, the minimum ENC is
is the largest value that keeps the input tran-
sistor in strong inversion. In the weak-inversion regime, a min-
imum value of ENC is achieved at
current equals the largest value that keeps the input transistor
in weak inversion. From Fig. 2, we can conclude that when the
biasing current is limited to 100
is preferred over the strong-inversion regime; when the biasing
current is higher, the strong-inversion regime becomes the pre-
eration of the input transistor is omitted in the comparison due
to the lack of tractable noise models.
and the biasing
, the weak-inversion regime
III. AMPLIFIER IMPLEMENTATION
The detailed circuit implementation of the amplifier, com-
prising a CSA and a pulse shaper, is outlined in this Section.
The optimization technique proposed in SectionII is appliedfor
sizing the input transistor.
A. Charge Sensitive Amplifier
Conventional architecture of the CSA with a high-gain am-
plifier and a small feedback capacitor for the input charge in-
tegration is implemented as the first stage of amplification. In
order to increase the overall gain provided by the input ampli-
fication stage, a two-stage cascaded charge-sensitive amplifier
is implemented, as shown in Fig. 5. To ensure high linearity of
the first-stage of the CSA, a pole-zero compensation network
is formed by a parallel connection of
back network formed by capacitor
second CSA stage increases the overall gain by a factor of
leading to the total gain of
plementation. The value of the DC voltage at the input of both
high-gain amplifiers is designed to be the same, so as to pro-
vide equal biasing conditions for transistors
which is necessary for the high linearity of the CSA. The choice
of feedback capacitors is influenced by the high detector capac-
itance; the feedback capacitors are set at
Fig. 6 shows the folded-cascode implementation of the high-
gain amplifier in the first stage of CSA. The PMOS input tran-
sistor is chosen over NMOS due to its lower flicker noise. The
replicas of the feed-
and transistor. The
in the proposed im-
Fig. 5. Cascaded CSA implementation.
Fig. 6. Folded-cascode with cascaded source follower as a high-gain amplifier
in the CSA.
. We found by simulation that the DC gain of the folded-cas-
code amplifier is 94 dB. The feedback transistor
in the subthreshold regime due to the low (10 pA) leakage cur-
rent of the detector.
1) Noise Contributions From Other Transistors: The addi-
tional noise contributions from
, and can be approx-
the gates of
namic resistance seen at the source node of
ferred voltage noise from
rent, and NMOS transistors have at least one order of magni-
tude higher flicker noise coefficient than PMOS, the noise con-
cannot be neglected. To reduce the thermal
has to be small, which leads to a higher
voltage drop for the fixed biasing current. To reduce the flicker
, the length of the transistor is increased .
can be neglected due to the large resistance
The optimization procedure presented in Section II is adjusted
to take into account the additional noise sources from (25).
2) Stability Analysis: The large input transistor makes the
non-dominant pole located at the folding node close to the dom-
inant pole located at the output of the folded-cascode amplifier;
are the input-referred noise sources at
and , respectively, andis the dy-
. The input-re-
is scaled by the transcon-
have similar biasing cur-
2134 IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 58, NO. 4, AUGUST 2011
thus, the stability of the CSA requires careful examination .
Assuming that the source follower is an ideal buffer and that the
reset MOS transistor
has a very large equivalent resistance
, the open-loop circuit can be modeled as shown in Fig. 7,
total capacitance at the folding node;
and; is the capacitance at the output of the
folded cascode amplifier and
output. Thus, the loop gain can be derived as:
is the resistance of cas-
is the capacitance at the CSA
where zero and poles are located at
We attribute pole
capacitive load, while
with the voltage amplifier. The feed-forward zero comes from
feedback network. The unity-gain frequency
to the feedback capacitor and the input
and are the two poles associated
phase contribution can be approximately canceled. Therefore,
the first non-dominant pole
mines the phase margin of the loop. It is reasonable to assume
that the CSA’s non-dominant pole is fixed, thus it is desirable to
far away from. A smaller
stable; however a large amplifier gain is required due to a high
ratio. Thus, adding a compensation capacitive load to
is the only feasible option. In our design, the value of
is 2 pF and the achieved phase margin is over 70 . Though the
added compensation capacitor slows the circuit’s step response
to over 3
, a time constant of 100
means that the overall readout system is not affected.
is critical and ultimately deter-
makes the CSA more
of the following shaper
Fig. 8. (a) Implementation of the pulse shaper. (b) Schematic of ICON cell.
Since the input capacitance of the second high-gain amplifier
in Fig. 5 is significantly smaller than that for the first amplifier,
sion of the first amplifier. The additional compensation capac-
itor is not required for the second amplifier.
B. Pulse Shaper
The calculated optimum shaping time constant for the pro-
posed amplifier is fairly large, 100
high capacitance and the low leakage current of the detector.
This time constant requires that there be no more than 30,000
photons/sec incident on a pixel. In order to achieve such a long
shaping time with the constraints of area and power, we have
chosen a filter based on ICON RC cell  that provides both
the low-area and the low-power shaper implementation. The
schematic of the two stage pulse shaper is shown in Fig. 8(a).
The ICON cell, shown in Fig. 8(b), makes the equivalent re-
times higher than the integrated physical resistance
due to the ratio of
in the current mirrors. The amplifiers in
the shaper are a scaled down version of the high-gain amplifier
in the CSA, thus ensuring the same amplifier DC level.
, as a consequence of the
The proposed readout system was implemented in 0.5
CMOS technology with the measured flicker-noise parameter
of the PMOS transistor equal to
of a single channel is 1.1 mm
of the implemented preamplifier was conducted at 3.3 V supply
The fabricated preamplifier is characterized without a sensor.
The chip-on-board technique was employed to wire-bond the
. Fig. 9 shows
0.4 mm. The characterization
YUN et al.: LOW-POWER AMPLIFIER FOR READOUT INTERFACE OF SEMICONDUCTOR SCINTILLATOR2135
Fig. 9. Microphotoofthe implementedsinglepreamplifier channel,containing
CSA and pulse shaper, in 0.5?? CMOS technology.
Fig. 10. Measured output voltage of the CSA for different values of the input
die directly on the printed circuit board. A 1 pF capacitor that
is connected externally to the input of the CSA enables a con-
trolled charge injection into the readout circuitry, as the current
pulse at the input is generated by applying a known voltage
step signal to the capacitor. A dc current is injected into the
input node of the CSA through a 1
through an on-board DAC. To model sensors capacitance in the
characterization of the noise performance of the preamplifier,
different external capacitors were used at the input node.
Fig. 10 shows the response of the CSA for different voltage
steps that correspond to the total input injected negative charge
of either 5000 or 10,000 or 20,000 electrons. Due to the small
leakage current of the detector and biasing of the feedback tran-
sistor in the subthreshold regime, the decay time of the CSA is
on the order of milliseconds. Fig. 11 shows the measured output
The measured charge gain is 71 mV/fC. The measured linearity
of the CSA is 0.4%, while the measured linearity of the ampli-
fier, consisting of the CSA and the pulse shaper, is 1.3%. A plot
of the output voltage of the amplifier as function of the input
charge is shown in Fig. 12.
The measure of the chip sensitivity is ENC. The measured
r.m.s. ENC (for the detector capacitance fixed at 50 pF and
the leakage current fixed at 10 pA) is 950 electrons, a higher
value than predicted. The minimum detectable signal of 3000
electrons corresponds to gamma energy resolution of 15 keV.
capacitance andthemeasuredslope is 18
power consumption of a single channel is 210
mance of the implemented amplifier is matched to the required
minimum detectable signal and the input range of the proposed
resistor and is controlled
. The perfor-
Fig. 11. Measured output voltage of the pulse shaper for different values of the
Fig. 12. Measured output voltage of the amplifier as a function of the input
Fig. 13. Measured ENC as a function of the input capacitance.
We presented the design and the implementation of a low-
noise, low-power amplifier to register the semiconductor scin-
tillator signal excited by ionizing radiation. To increase the sen-
sitivity of the readout circuitry under the area, power and event-
and applied it to the design of the CSA. The integration of the
proposed readout amplifier and semiconductor scintillator in a
3D array will provide both isotope discrimination and angular
resolution in various homeland security applications.
2136 IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 58, NO. 4, AUGUST 2011 Download full-text
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(Brookhaven National Lab) for useful discussions and re-
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