Conference Proceeding

Enhanced IEEE 1500 test wrapper for testing small RAMs in SOCs

Dept. of Electr. Eng., Nat. Central Univ., Jhongli, Taiwan
10/2010; DOI:10.1109/SOCC.2010.5784742 pp.236 - 240 In proceeding of: SOC Conference (SOCC), 2010 IEEE International
Source: IEEE Xplore

ABSTRACT IEEE 1500 test wrapper wraps logic cores in system-on-chips (SOCs) for the core test and isolation. On the other hand, random access memory (RAM) cores are typically tested using the built-in self-test (BIST) circuit instead of using the IEEE 1500 test wrapper. But, RAM cores are usually connected to logic cores. This paper proposes an enhanced IEEE 1500 test wrapper to support the testing of the RAM core attached to the test wrapper. Furthermore, the memories attached to the enhanced IEEE 1500 test wrappers can be tested in parallel. Simulation results show that the additional area cost for upgrading the IEEE 1500 test wrapper to an enhanced one is only about 0.88% for a 1024 × 64-bit RAM.

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Keywords

additional area cost
 
built-in self-test
 
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memories
 
random access memory
 
Simulation results
 
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