Enhanced IEEE 1500 test wrapper for testing small RAMs in SOCs
ABSTRACT IEEE 1500 test wrapper wraps logic cores in system-on-chips (SOCs) for the core test and isolation. On the other hand, random access memory (RAM) cores are typically tested using the built-in self-test (BIST) circuit instead of using the IEEE 1500 test wrapper. But, RAM cores are usually connected to logic cores. This paper proposes an enhanced IEEE 1500 test wrapper to support the testing of the RAM core attached to the test wrapper. Furthermore, the memories attached to the enhanced IEEE 1500 test wrappers can be tested in parallel. Simulation results show that the additional area cost for upgrading the IEEE 1500 test wrapper to an enhanced one is only about 0.88% for a 1024 × 64-bit RAM.
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ABSTRACT: This work describes a modular design of a wrapper enabling BIST/BISR for small memories operating as register files or FIFOs in high speed applications such as graphics and networking. The wrapper allows for at-speed test at low overhead and enables a simple repair scheme when millions of bits are used in such memories. The wrapper is intended to provide a standardized interface between memory and test controller, and thus work with any BIST controller, and communication between the two is minimized and at a reduced frequency.Test Conference, 2004. Proceedings. ITC 2004. International; 11/2004
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ABSTRACT: Memory testing is becoming the dominant factor in test- ing a system-on-chip (SOC), with the rapid growth of the size and density of embedded memories. To minimize the test effort, we present an automatic generation framework of memory built-in self-test (BIST) cores for SOC designs. The BIST generation framework is a much improved one of our previous work. Test integration of heterogeneous memory architectures and clusters of memories are focused. The au- tomatic test grouping and scheduling optimize the overhead in test time, performance, power consumption, etc. Further- more, with our novel BIST architecture, the BIST cores can be accessed via an on-chip bus interface (e.g., AMBA), which eases the control of testing and diagnosis in a typical SOC scenario. With a configurable and extensible architecture, the proposed framework facilitates easy memory test inte- gration for core providers as well as system integrators.10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan; 01/2001
Conference Paper: Test scheduling of BISTed memory cores for SoC[Show abstract] [Hide abstract]
ABSTRACT: The test scheduling of memory cores can significantly affect the test time and power of system chips. We propose a test scheduling algorithm for BISTed memory cores to minimize the overall testing time under the test power constraint. The proposed algorithm combines several approaches for a near-optimal result, based on the properties of BISTed memory cores. By proper partitioning, an analytic exhaustive search finds optimal results for large memory cores, while a heuristic ordering with simulated annealing further handles a large amount of smaller memory cores. On the average, the results are within 1% difference of the optimal solution for the cases of 200 memory cores.Test Symposium, 2002. (ATS '02). Proceedings of the 11th Asian; 12/2002