Enhanced IEEE 1500 test wrapper for testing small RAMs in SOCs
ABSTRACT IEEE 1500 test wrapper wraps logic cores in system-on-chips (SOCs) for the core test and isolation. On the other hand, random access memory (RAM) cores are typically tested using the built-in self-test (BIST) circuit instead of using the IEEE 1500 test wrapper. But, RAM cores are usually connected to logic cores. This paper proposes an enhanced IEEE 1500 test wrapper to support the testing of the RAM core attached to the test wrapper. Furthermore, the memories attached to the enhanced IEEE 1500 test wrappers can be tested in parallel. Simulation results show that the additional area cost for upgrading the IEEE 1500 test wrapper to an enhanced one is only about 0.88% for a 1024 × 64-bit RAM.
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ABSTRACT: This paper proposes an enhanced IEEE 1500 test wrapper to support the testing and diagnosis of the single-port or multi-port RAM core attached to the enhanced IEEE 1500 test wrapper without incurring large area overhead to small memories. Effective test time reduction techniques for the proposed test scheme are also proposed. Simulation results show that the additional area cost for implementing the enhanced IEEE 1500 test wrapper is only about 0.58% for a 64 K-bit single-port RAM and only 0.57% for a 64 K-bit two-port RAM in 90-nm technology.IEEE Transactions on Very Large Scale Integration (VLSI) Systems 11/2012; 20(11):2123-2127. DOI:10.1109/TVLSI.2011.2165568 · 1.14 Impact Factor