Speeding Up Emulation-Based Diagnosis Techniques for Logic Cores

IEEE Design and Test of Computers (Impact Factor: 1.62). 09/2011; DOI: 10.1109/MDT.2011.25
Source: IEEE Xplore

ABSTRACT This article proposes a new approach for an FPGA-based emulation system for IC fault diagnosis that incorporates three speedup techniques: circuit partitioning, fault-injection elements (using a novel design), and a fault-injection scan chain. Experimental results in terms of hardware overhead and emulation time for ISCAS-85 benchmark circuits are compared with previous works to highlight the 33× speedup and 44% reduced overhead of this proposed system.

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    ABSTRACT: In this paper, a novel approach is introduced on accelerating the fault simulation speed on field programmable gate array (FPGA). The approach is based on parallel simulation methodology. More than one faulty circuit is handled in the fault simulation system, but the relative area overhead is low and it will accelerate the simulation process. A new metrics - Speedup relative to the Ratio of Hardware Overhead (SRHO) is introduced, by which the experimental results are evaluated. Experimental results in terms of simulation time, hardware overhead and SRHO for ISCAS-85 benchmark circuits are compared to a previous work to show its advantage. (C) 2011 Published by Elsevier Ltd. Selection and/or peer-review under responsibility of [CEIS 2011]
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