Speeding Up Emulation-Based Diagnosis Techniques for Logic Cores

IEEE Design and Test of Computers (Impact Factor: 1.62). 09/2011; DOI: 10.1109/MDT.2011.25
Source: IEEE Xplore

ABSTRACT This article proposes a new approach for an FPGA-based emulation system for IC fault diagnosis that incorporates three speedup techniques: circuit partitioning, fault-injection elements (using a novel design), and a fault-injection scan chain. Experimental results in terms of hardware overhead and emulation time for ISCAS-85 benchmark circuits are compared with previous works to highlight the 33× speedup and 44% reduced overhead of this proposed system.

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