A 65nm 2.97GHz self Synchronous FPGA with 42% power bounce tolerance
ABSTRACT The performance and robustness to PVT variations has been measured of an improved Self Synchronous FPGA (SSFPGA) designed in 65 nm CMOS which achieves 2.97 GHz throughput at 1.2V. The proposed SSFPGA employs a 38×38 array of 4-input, 3-stage Self Synchronous Configurable Logic Blocks, with the introduction of a new dual tree-divider 4 input LUT to achieve a 4.5× throughput improvement over the previous model , . Correct operation is measured with 500 mVp-p, 1.12 GHz externally introduced power supply noise at 1.2V power supply, equivalent to 42% power supply bounce. Sensitivity against power supply noise frequency has been measured, and showed a strong correlation with the average operating frequency. Correct operation for 10 chips that show 16% performance variation, with VDD change from 728 mV to 1.6V, and temperature change from 0 to 80°C, without altering any input parameters such as clock frequency. Results show the SSFPGA can adapt and is inherently robust to these variations with a internal throughput measured ranging from 300 MHz to 4.07 GHz, while maintaining correct operation.