Experimental study on carrier transport limiting phenomena in 10 nm width nanowire CMOS transistors

Abstract

For the first time, we experimentally analyze the limiting scattering phenomena in gate-all-around nanowire CMOS transistors with aggressive dimensions (L_eff of 32 nm for NMOS and 42 nm for PMOS with 15 nm nanowire width) and with high-k/metal gate stacks. One-level and multiple-level stacked nanowire structures are measured and compared. The apparent carrier mobility is degraded in short channel devices. Moreover, we show that the interface quality has a major impact on nanowire transport properties. In rounded nanowires (thanks to H₂ anneal), the extracted coulomb-limited mobility decreases whereas the surface roughness-limited mobility increases. Additionally, stacked nanowires suffer from additional coulomb scattering which is attributed to a degraded interface with high-k.

Full text

Page 1

Experimental study on carrier transport limiting phenomena
in 10 nm width nanowire CMOS transistors

K. Tachi1, 2, 4, M. Cassé1, S. Barraud1, C. Dupré1, A. Hubert1, N. Vulliet3, 1, M.E. Faivre1, C. Vizioz1,
C. Carabasse1, V. Delaye1, J.M. Hartmann1, H. Iwai4, S. Cristoloveanu2, O. Faynot1 and T. Ernst1

1CEA-LETI, MINATEC, 17 avenue des Martyrs 38054 Grenoble Cedex 9, France,
2IMEP-LAHC, INPG-MINATEC, 3 Parvis Louis Neel, 38016 Grenoble Cedex 1, France,
3STMicroelectronics, 850 rue J. Monnet, 38926 Crolles Cedex, France,
4Frontier Research Center, Tokyo Institute of Technology, 4259, Nagatsuta, Midori-ku, Yokohama, 226-8502, Japan
Phone: +33 4 38 78 02 10, Fax: +33 4 38 78 30 34, e-mail: k.tachi@iwailab.ep.titech.ac.jp or thomas.ernst@cea.fr

Abstract

For the first time, we experimentally analyze the limiting
scattering phenomena in gate-all-around nanowire CMOS
transistors with aggressive dimensions (Leff of 32 nm for
NMOS and 42 nm for PMOS with 15 nm nanowire width)
and with high-k/metal gate stacks. One-level and multiple-
level stacked nanowire structures are measured and compared.
The apparent carrier mobility is degraded in short channel
devices. Moreover, we show that the interface quality has a
major impact on nanowire transport properties. In rounded
nanowires (thanks to H2 anneal), the extracted coulomb-
limited mobility decreases whereas the surface roughness-
limited mobility increases. Additionally, stacked nanowires
suffer from additional coulomb scattering which is attributed
to a degraded interface with high-k.

Introduction

Gate-all-around (GAA) silicon nanowire transistors (SNWTs)
are one of the best structures to suppress short channel effects
(SCEs) [1]. Recently, many GAA SNWTs have successfully
been fabricated with very short channel lengths and small
diameters by several top-down CMOS compatible processes
[2-5]. Transport property degradations in nanowires with sub-
10 nm diameter were reported by several groups [6-8].
However, it is possible to combine high performances and
SCE immunity in sub-15nm gate length NWs with diameter
varying from 20 nm down to 10 nm [5, 8]. Transport limiting
phenomena have recently been studied in n-type SiO2/Poly-Si
SNWTs with diameters in the 15 to 50 nm range and long
gate lengths [9]. Hole behaviour and the high-k impact on
NW transistor are however still unknown. Moreover, in the
quasi-ballistic transport regime, carrier mobility is still an
important parameter [10]. Mobility limiting components,
such as coulomb scattering, phonon scattering, and surface-
roughness scattering, have hardly been investigated
experimentally. To evidence those phenomena, we have thus
studied the ballistic transport properties and the mobility
limiting factors in SNWTs by low temperature measurements
down to 5 K.

Device Structure

Multiple -stacked SNWTs were fabricated on (100) SOI
wafers by top-down CMOS process with epitaxially-grown
Si/SiGe layers. Superior on-state currents per surface unit
have been achieved in those devices, whose cross-sectional
TEM and SEM images can be found in Fig. 1. Fabrication
details were provided in [8, 11]. The width (WNW) of
rectangular shape nanowire ranges from 10 nm up to 30 nm
and the height (HNW) is 15 nm. We also fabricated 1-level
SNWTs by thermal oxidation and removal of its oxide (i.e.
without SiGe epitaxy and selective etching) as shown in Fig.1
(a). H2 annealing enabled us to obtain 1-level SNWTs with a
circular cross-section [8, 12]. The resulting equivalent oxide
thickness (EOT) is ~1.7 nm (3nm-thick-HfO2 and 10nm-
thick-TiN gate stack). All measured NWs are [110]-oriented
LNW
WNW
WNW
(a)(a)
100nm
(b)(b)
10nm10nm
HNW
(d)(d)
SourceSourceDrainDrain
NWsNWs
42 nm42 nm
(c) (c)
100nm100nm
LNW
100nm
HNW

Figure 1: Cross-sectional Transmission Electron Microscopy and Scanning Electron Microscopy images of our SNWTs; (a) cross-section along the
nanowire width for one-level SNWTs, (b) cross-section along the nanowire width for multiple-stacked SNWTs, (c) the enlarged image of a rectangular
nanowire with a high-k/metal gate stacks, and (d) cross-section along the nanowire for multiple-stacked nanowire with 42 nm length before conformal
gate stack deposition.

Page 2

and horizontally arrayed with 50 parallel wires. The physical
wire lengths (LNW) are in the 42 – 607 nm range. Effective
gate length (Leff) and source/drain resistance (RSD) were
extracted thanks to the Y-function-based technique [13, 14].
Differences between LNW and Leff were less than 10 nm. This
means that the source/drain implantation and activation
annealing are well-controlled. Resulting RSD are 159 Ω.µm
for NMOS and 161 Ω.µm for PMOS.

Basic Characteristics and Ballistic Transport Properties

The measured IDS-VDS (Fig.2) and IDS-VGS (Fig.3)
characteristics for multiple-stacked 15 nm width SNWTs
with 32 nm effective gate length (Leff) for NMOS and 42 nm
for PMOS show well-behaved characteristics. IDS-VGS curves
exhibit an excellent subthreshold slope (64 mV/dec for
NMOS and 74 mV/dec for PMOS) and very low Drain
Induced Barrier Lowering (32mV/V for NMOS and 62 mV/V
for PMOS). On-currents ION (normalized by total
circumference) of 840 µA/µm and 540 µA/µm with IOFF of 4
nA/µm and 96 nA/µm are obtained for NMOS and PMOS,
respectively. Comparable results were obtained in fully-
depleted SOI and 1-level-SNWTs [2, 15]. When the currents
are normalized by top-view width, the ION for NMOS is 7.2
mA/µm for 3D-stacked nanowires and 2.6 mA/µm for one-
level, showing the interest of 3D devices to increase current
density for a given layout. These extremely high currents are
due to the vertically stacked structure. Fig. 4 shows ION as a
function of Leff. Gate length scaling is still effective down to
sub-50nm Leff. Meanwhile, low field mobility (µ0) is
degraded with decreasing Leff as shown in Fig. 5. One of the

PMOS
1.2
IDS[mA/µm]
0.4
0.2
0.0
possible reasons is the ballistic motion of carriers. The
mobility experimentally extracted can be limited by ballistic
transport. Indeed, mobility is defined as the ratio between the
drift velocity and the electric field [16]. Thanks to the
temperature dependence of both saturation velocity (vsat) and
injection velocity (vinj), the nature of the transport can be
evidenced by plotting the temperature dependence of the
limiting velocity defined by vlim = min (vsat, vinj) [17]. The
temperature dependence of IDS-VGS curves for the SNWT
with Leff of 32 nm is shown in Fig. 6. The temperature range
is from 5 to 300 K. The threshold voltage (VT) decreases with
temperature, while the sub-threshold slope (SS) increases.
These changes in VT and SS with temperature are mainly due
to band gap changes and are consistent with the theory. Fig. 7
shows temperature dependence of vlim for NMOS. It is clear
that long SNWTs are almost exclusively vsat limited.
Meanwhile, vinj slightly affects vlim in short channel (Leff = 32
nm) SNWTs.

Mobility Lowering Components

Since the backscattering rate is directly related to the mobility,
it is important to examine the temperature dependence of
mobility to quantify the contribution of each scattering
mechanism. In order to accurately evaluate the transport
properties, the effective mobility (µeff) was extracted by split
C-V technique with parasitic capacitance and RSD corrections
[18]. Fig. 8 shows the validity of the extraction. A good
agreement when compared to other techniques was achieved
[19].
NMOSNMOS
0.00.00.50.51.01.0-0.5-0.5-1.0-1.0
VDS[V]VDS[V]
1.41.4
1.2
1.0
0.8
0.6
0.4
0.2
1.0
0.8
0.6
0.0
|VG-VT| : 0 to 0.9 V
Step: 0.05 VStep: 0.05 V
PMOS
IDS[mA/µm]
|VG-VT| : 0 to 0.9 V

PMOSPMOS NMOSNMOS
10-1
10-3
10-5
10-7
10-9
10-11
10-13
10-15
10-15
VDS= -1VVDS= -1V
VDS= -50mV
VDS= -50mV
VDS= 1V
VDS= 1V
VDS= 50mV
VDS= 50mV
001122-1 -1-2 -2
VG[V] VG[V]
IDS[A/µm]
Leff=32nm
ION=840µA/µm
ION/IOFF~2x105
VTsat=0.5V
SS=64 mV/dec
DIBL=32mV/V DIBL=32mV/V
Leff=42nm
ION=540µA/µm
ION/IOFF~6x103
VTsat=-0.37V
SS=73 mV/dec
DIBL=63mV/V DIBL=63mV/V
10-1
10-3
10-5
10-7
10-9
10-11
10-13
IDS[A/µm]
Leff=32nm
ION=840µA/µm
ION/IOFF~2x105
VTsat=0.5V
SS=64 mV/dec
Leff=42nm
ION=540µA/µm
ION/IOFF~6x103
VTsat=-0.37V
SS=73 mV/dec
PMOSPMOS
NMOSNMOS
0.10.1110.010.01
Leff[µm]Leff[µm]
1.01.0
ION[mA/µm] 0.8
0.60.6
0.40.4
0.00.0
|VDS| = 1 V
|VG-VT| = 0.7 V
|VG-VT| = 0.7 V
0.20.2
ION[mA/µm] 0.8
|VDS| = 1 V
Figure 2: ID-VD characteristics of multiple-
stacked Leff = 32 nm NMOS and Leff = 42 nm
PMOS SNWTs. The WNW and HNW are 15nm.
Currents are normalized by the circumference
(Wtot).
300 300
Figure 3: ID-VG characteristics of multiple-
stacked Leff = 32 nm NMOS and Leff = 42 nm
PMOS SNWTs. The WNW and HNW are 15nm.
Currents are normalized by the circumference
(Wtot).
10-1
T = 5K, 50K, 100K, 150K,
200K, 250K, RT
10-3
200K, 250K, RT
Figure 4: On-currents ION for NMOS and PMOS
as a function of Leff.
PMOSPMOS
NMOSNMOS
0.10.1110.010.01
Leff[µm]Leff[µm]
µ0[cm2/V.s]250
200 200
150 150
00
|VDS| = 10 mV
|VDS| = 10 mV
100100
50 50
µ0[cm2/V.s]250

NMOS
VDS= 1V
Leff= 32 nm
Leff= 32 nm
10-3
10-5
10-5
10-7
10-7
10-9
10-9
10-11
10-11
10-13
10-13
001122-1-1
VG[V]VG[V]
IDS[A]
RTRT
Low TLow T
NMOS
VDS= 1V
10-1
IDS[A]
T = 5K, 50K, 100K, 150K,
200 200300 30010010000
T [K]T [K]
Normalized vlim
1.21.2
1.01.0
0.80.8
vinjtemperature
dependencedependence
vsattemperature
dependencedependence
@Ninv=1x1013cm-2
vinjtemperature
1.41.4
1.61.6
⎟⎟
⎠⎠
⎞
⎟⎟
⎜⎜
⎝⎝
⎛
⎜⎜
−−
∂∂
∂
V
vsattemperature
==
linlinONON GTGT
LLLL
μμμμνlim
νlim
11
Leff=32nm
Leff=92nm
Leff=242nm
Leff=242nm
Leff=242nm
Normalized vlim
@Ninv=1x1013cm-2
⎞
⎛
∂
V
Leff=32nm
Leff=92nm
Leff=92nm
Leff=32nm
Figure 5: Low field mobility µ0 for NMOS and
PMOS as a function of Leff. The mobility was
extracted with the Y-function-based technique.
Figure 6: Temperature dependence of ID-VG
characteristics for multiple-stacked SNWTs.

Figure 7: Temperature dependence of vlim
extracted with the equation provided in the insert
[17].

Page 3

Fig. 9 and 10 show effective mobility for electrons and holes
in vertically stacked SNWTs as a function of inversion
charge density (Ninv) at different temperatures. It is clear that
the electron mobility dependence on temperature is much
lower than for hole. In general, mobility in MOSFETs is
limited by three scattering components; coulomb, phonon,
and surface roughness as shown in Fig. 11. The coulomb-
(µcb) and phonon-(µph) limited mobilities have negative and
positive contribution at low temperature, respectively.
Meanwhile, the surface roughness-limited mobility (µsr) does
not depend on temperature. At low temperature, mobility is
limited by only the coulomb scattering only at low Ninv and
only by the surface-roughness scattering only at high Ninv.
Figs. 12 and 13 show effective mobility for electron and hole
at high Ninv as a function of temperature for different WNW,
respectively. Electron and hole surface roughness-limited
mobility µsr is degraded when WNW decreases, while the
temperature dependence of µph does not depend on WNW as
shown in Fig. 14 and 15. On the other hand, in Fig. 16,
electron mobility at low Ninv is degraded at lower
temperatures. This indicates that the electron mobility in
vertically stacked SNWTs is strongly limited by coulomb
scattering, while the hole mobility is mainly limited by
surface roughness scattering as shown in Fig. 17. Moreover,
coulomb scattering is more dominant in wider nanowires for
electrons than for holes. Fig. 18 shows a mobility comparison
between multiple-stacked and 1-level SNWTs with 15 nm of
WNW. In the case of 1-level SNWTs, coulomb scattering is
less dominant. The effective
dependence for 1-level SNWTs is consistent with the
reported µeff behavior in SNWTs [8]. The reason why
stronger coulomb scattering is higher in stacked SNWTs may
be the degraded interface quality with high-k because of the
use of SiGe sacrificial layers. Additional surface treatments
may thus be needed.
mobility temperature
1.01.01.51.5220.5 0.5 0.00.0
VG[V]VG[V]
300300
Electron µeff[cm2/V.s]
200 200
100100
00
Split C-V w RSDcorrection
Double LmMethod
Y-function methodY-function method
Electron µeff[cm2/V.s]
Split C-V w RSDcorrection
Double LmMethod

Leff=532nmLeff=532nm
0.20.21.01.00.00.0
Ninv[x 1013cm-2]Ninv[x 1013cm-2]
300300
Electron µeff[cm2/V.s]
200200
00
100100
0.40.40.60.60.80.8
T = 5K, 100K, 200K, 300KT = 5K, 100K, 200K, 300K
Low TLow T
High THigh T
Electron µeff[cm2/V.s]
Leff=542nmLeff=542nm
0.20.2 1.01.0 0.00.0
Ninv[x 1013cm-2]Ninv[x 1013cm-2]
300300
Hole µeff[cm2/V.s]
200200
00
100100
0.40.4 0.6 0.60.80.8
T = 5K, 100K, 200K, 300KT = 5K, 100K, 200K, 300K
Low T Low T
High THigh T
Hole µeff[cm2/V.s]
Figure 8: Comparison of effective mobility
extracted by split C-V, double Lm method, and
from parameters extracted by Y-function method.
The measured device is the stacked SNWTs with
WNW=15 nm and Leff=242 nm. The device with
Leff=592 nm was also used for double Lm method.
11
=
cbeff
μμ
Figure 9: Effective electron mobility as a
function of inversion charge density for multiple-
stacked SNWTs with WNW=15 nm and Leff=532
nm for different temperatures from 300 K down
to 5 K.

Electron µeff[cm2/V.s]
101
100
Figure 10: Effective hole mobility as a function
of inversion charge density for multiple-stacked
SNWTs with WNW=15 nm and Leff=542 nm for
different temperatures from 300 K down to 5 K.
Ninv
Ninv
µeff
µeff
µsr
µsr
µph
µph
µcb
µcb
Low TLow T
Low TLow T
srsrphph cbeff
μμμμμμ
1111
++++
11
=

101
103
103
100
T [K]T [K]
300300
200200
100100
102
102
400400
@ Ninv=1x1013cm-2
@ Ninv=1x1013cm-2
WNW=30nm
WNW=20nm
WNW=15nm
WNW=10nm
WNW=10nm
WNW=10nm
Electron µeff[cm2/V.s]
WNW=30nm
WNW=20nm
WNW=15nm
WNW=15nm
WNW=30nm
WNW=20nm
101
101
103
103
100
100
T [K]T [K]
300300
Hole µeff[cm2/V.s]
200200
100100
102
102
400400
@ Ninv=1x1013cm-2
@ Ninv=1x1013cm-2
WNW=30nm
WNW=20nm
WNW=15nm
WNW=10nm
WNW=10nm
Hole µeff[cm2/V.s]
WNW=30nm
WNW=20nm
WNW=15nm
Figure 11: Schematic illustration of mobility
limiting factors with temperature. As temperature
decreases, µph increases while µcb decreases.
Electron µph [cm2/V.s]
102
101
Figure 12: Effective electron mobility at high
Ninv as a function of temperature for different
WNW. The µeff at 5 K can be regarded as the µsr.
104
WNW=30nm
WNW=20nm
WNW=15nm
WNW=10nm
103
Figure 13: Effective hole mobility at high Ninv as
a function of temperature for different WNW
103
103
101
T [K]T [K]
103
103
102
102
104
104
WNW=30nm
WNW=20nm
WNW=15nm
WNW=10nm
WNW=10nm
WNW=10nm
∝T-1.75
∝T-1.75
@ Ninv=1x1013cm-2
@ Ninv=1x1013cm-2
Electron µph [cm2/V.s]
102
WNW=30nm
WNW=20nm
WNW=15nm
WNW=15nm
WNW=30nm
WNW=20nm
103
103
101
101
T [K]T [K]
Hole µph [cm2/V.s]
103
102
102
102
102
∝T-1.75
∝T-1.75
@ Ninv=1x1013cm-2
@ Ninv=1x1013cm-2
Hole µph [cm2/V.s]
104
WNW=30nm
WNW=20nm
WNW=15nm
WNW=10nm
101
101
103
103
100
100
T [K]T [K]
300300
Electron µeff[cm2/V.s]
200200
100100
102
102
400400
@ Ninv=2 x 1012cm-2
@ Ninv=2 x 1012cm-2
WNW=30nm
WNW=20nm
WNW=15nm
WNW=10nm
WNW=10nm
Electron µeff[cm2/V.s]
WNW=30nm
WNW=20nm
WNW=15nm
Figure 14: Phonon-limited electron mobility at
high Ninv as a function of temperature for
different WNW.
Figure 15: Phonon-limited hole mobility at high
Ninv as a function of temperature for different
WNW.
Figure 16: Effective electron mobility at low Ninv
as a function of temperature for different WNW.

Page 4

The impact of H2 annealing on NW surface quality was
investigated. Fig. 19 shows that IDS-VGS curves of 1-level
SNWTs with and without H2 annealing at 300 K and 5 K. The
same curve is obtained at 300 K, while, at 5 K, degradation in
the threshold region is observed in the H2-annealed SNWTs.
Figs. 20-22 show the comparison of effective electron
mobility. It is clear that effective mobility in H2-annealed
SNWTs is more degraded by coulomb scattering, while
surface roughness is improved. This coulomb scattering
degradation is consistent with our previous work, which
evidenced the increase of interface trap density on rounded
nanowires [20].

Conclusion

The optimisation of short-channel CMOS nanowire drive
current will have to take into account specific effects. In
particular, additional scattering observed in rounded wires
can limit ballisicity and thus the ION current. Additional work
on interface optimization and passivation is thus needed on
NW structures.

Acknowledgement

This work was performed as part of the IBM-STMicro-
electronics-CEA/LETI-MINATEC Development Alliance.



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101
101
103
103
100
100
T [K]T [K]
300300
Hole µeff[cm2/V.s]
200 200
100100
102
102
400400
@ Ninv=2x1012cm-2
@ Ninv=2x1012cm-2
WNW=30nm
WNW=20nm
WNW=15nm
WNW=10nm
WNW=10nm
Hole µeff[cm2/V.s]
WNW=30nm
WNW=20nm
WNW=15nm
101
101
103
103
100
100
T [K]T [K]
Electron µeff[cm2/V.s]
102
102
102
102
103
103
@ Ninv=2x1012cm-2
@ Ninv=2x1012cm-2
1-level-SNWT1-level-SNWT
multiple-stacked SNWTmultiple-stacked SNWT
Electron µeff[cm2/V.s]
T=5K T=5KT=300KT=300K
VG-VT[V]
VG-VT[V]
10-3
10-3
IDS[A]
10-4
10-4
10-6
10-6
0.00.00.4 0.4
0.8 0.8
0.0 0.00.4 0.4
0.8 0.8
10-5
10-5
10-7
10-7
10-8
10-8
10-9
10-9
w H2anneal
w/o H2anneal
w/o H2anneal
IDS[A]
w H2anneal
Figure 17: Effective hole mobility at low
Ninv as a function of temperature for different
WNW.
Figure 18: Effective electron mobility at low Ninv
as a function of temperature for 1-level-SNWT
and multiple-stacked SNWT.
Figure 19: ID-VG curves for 1-level-SNWTs with
and without H2 annealing at 300 K and 5 K.
0.20.21.01.00.00.0
Ninv[x 1013cm-2]Ninv[x 1013cm-2]
800 800
Electron µeff[cm2/V.s]
600600
00
400400
0.4 0.40.60.60.80.8
T = 5K, 100K, 200K, 300K T = 5K, 100K, 200K, 300K
200200
Open : w H2anneal
Solid : w/o H2anneal
Solid : w/o H2anneal
Low TLow T
High THigh T
Electron µeff[cm2/V.s]
Open : w H2anneal
101
101
103
103
100
100
T [K]T [K]
Electron µeff[cm2/V.s]
102
102
102
102
103
103
@ Ninv=2x1012cm-2
@ Ninv=2x1012cm-2
w H2anneal
w/o H2anneal
w/o H2anneal
w/o H2anneal
Electron µeff[cm2/V.s]
w H2annealw H2anneal
101
101
103
103
100
100
T [K]T [K]
Electron µeff[cm2/V.s]
102
102
102
102
103
103
@ Ninv=1x1013cm-2
@ Ninv=1x1013cm-2
w H2anneal
w/o H2anneal
w/o H2anneal
w/o H2anneal
Electron µeff[cm2/V.s]
w H2annealw H2anneal
Figure 20: Effective electron mobility as a
function of inversion charge density for 1-level-
SNWTs with and without H2 annealing for
different temperatures.
Figure 21: Effective electron mobility at
low Ninv as a function of temperature for 1-level-
SNWTs with and without H2 annealing.
Figure 22: Effective electron mobility at high
Ninv as a function of temperature for 1-level-
SNWTs with and without H2 annealing.