An Accurate Two-Port De-Embedding Technique for RF/Millimeter-Wave Noise Characterization and Modeling of Deep Submicrometer Transistors
ABSTRACT An accurate and simple noise de-embedding technique is proposed for high-frequency noise characterization of transistors. It is demonstrated on 0.13-μm CMOS devices for up to 80 GHz. The proposed technique adopts a generalized two-port fixture model in conjunction with a set of shielded based structures, which enable simple de-embedding of fixture parasitic for up to the Metal 1 level. Unlike other methods, it is capable of simultaneously accounting for the parasitic effects of probe to pad contact impedances and metal finger parasitic while using only three dummy test structures. Also, it is designed to accommodate nonsymmetry between bond pad parasitic elements at two-port without consuming additional silicon area. This corresponds to a reduction in noise de-embedding error, which increases along the frequency domain (6% of NFmin at 80 GHz). Meanwhile, underestimation of metal finger parasitic by conventional techniques has lead to degradation in noise performance (NFmin) of 0.13-μm CMOS transistors by more than 3.5 dB at 80 GHz. Further validation results from extracted gate capacitance and transistor gain performance provide solid support to the proposed de-embedding technique.
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ABSTRACT: Conventional on-wafer test fixtures have a significant impact on two-port noise-parameter measurements of silicon devices at gigahertz frequencies. This leads to increased measuring inaccuracy, as well as a need for complicated and area-consuming deembedding procedures. Alternatively, shield-based test fixtures are characterized by very few series effects and, thus, support cost-efficient and simple deembedding. The applicability of a simple one-step method is illustrated with experimental data. A performance comparison is made to full-scale deembedding methods based on conventional, as well as shield-based test fixtures.IEEE Transactions on Microwave Theory and Techniques 02/2003; · 2.23 Impact Factor
Conference Proceeding: General accuracy considerations of microwave on-wafer silicon device measurements[show abstract] [hide abstract]
ABSTRACT: This paper gives a general treatment of problems encountered when conducting microwave on-wafer measurements on devices fabricated on silicon substrates. First, issues specific to low-resistivity substrates and low-conductance metallization are detailed. This treatment includes probing reliability, contact resistance, leakage effects, and substrate coupling. Next, some widely disputed subjects of on-wafer measurements are assessed and novel techniques for verifying measuring accuracy are proposedMicrowave Symposium Digest. 2000 IEEE MTT-S International; 02/2000
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ABSTRACT: A general deembedding procedure using one “OPEN” and two “THRU” dummy structures for noise and scattering parameter deembedding based on cascade configurations is presented in this paper. This technique does not require any equivalent-circuit modeling of probe pads or interconnections. This deembedding procedure is valid for designs having interconnections with any kinds of geometries and for devices operated at frequencies of several tens of gigahertzIEEE Transactions on Microwave Theory and Techniques 06/2001; · 2.23 Impact Factor
IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 59, NO. 2, FEBRUARY 2011479
An Accurate Two-Port De-Embedding Technique
for RF/Millimeter-Wave Noise Characterization and
Modeling of Deep Submicrometer Transistors
Xi Sung Loo, Kiat Seng Yeo, Senior Member, IEEE, Kok Wai J. Chew, Member, IEEE, Lye Hock Kelvin Chan,
Shih Ni Ong, Manh Anh Do, Senior Member, IEEE, and Chirn Chye Boon
Abstract—An accurate and simple noise de-embedding tech-
nique is proposed for high-frequency noise characterization of
transistors. It is demonstrated on 0.13- m CMOS devices for
up to 80 GHz. The proposed technique adopts a generalized
two-port fixture model in conjunction with a set of shielded based
structures, which enable simple de-embedding of fixture parasitic
for up to the Metal 1 level. Unlike other methods, it is capable of
simultaneously accounting for the parasitic effects of probe to pad
contact impedances and metal finger parasitic while using only
three dummy test structures. Also, it is designed to accommodate
nonsymmetry between bond pad parasitic elements at two-port
without consuming additional silicon area. This corresponds to
a reduction in noise de-embedding error, which increases along
the frequency domain (6% of NFmin at 80 GHz). Meanwhile,
underestimation of metal finger parasitic by conventional tech-
niques has lead to degradation in noise performance (NFmin)
of 0.13- m CMOS transistors by more than 3.5 dB at 80 GHz.
Further validation results from extracted gate capacitance and
transistor gain performance provide solid support to the proposed
Index Terms—Layout, MOSFETs, scattering parameters, semi-
conductor device noise.
the vicinity of 100-GHz frequency. As a consequence, high-fre-
quency noise has emerged as a dominant issue in RF integrated
circiut (RFIC) design, which is further worsened by scaling of
power supply and increase in complexity of RF circuits. This
drives the need for precise transistor noise model, which re-
lies greatly on accurate high-frequency noise characterization
of the transistor device. A robust noise de-embedding technique
is therefore essential to correctly extract the intrinsic noise pa-
rameters of the transistor device by completely removing sur-
rounding parasitic noise effects of the test fixture. However, the
dominance of fixture parasitic effects as a result of drastic re-
APID advancement in wireless technology over the past
few decades has pushed transistor devices to operate in
Manuscript received June 26, 2010; revised September 24, 2010; accepted
November 03, 2010. Date of publication January 10, 2011; date of current ver-
sion February 16, 2011.
X. S. Loo, K. W. J. Chew, and S. N. Ong are with VIRTUS, Integrated Cir-
cuit (IC) Design Centre of Excellence, School of Electrical and Electronic En-
gineering, Nanyang Technological University, Singapore 639798, and also with
GLOBALFOUNDRIES Singapore Pte Ltd., Singapore 738406.
K. S. Yeo, L. H. K. Chan, M. A. Do, and C. C. Boon are with VIRTUS,
Integrated Circuit (IC) Design Centre of Excellence, School of Electrical and
Electronic Engineering, Nanyang Technological University, Singapore 639798.
Digital Object Identifier 10.1109/TMTT.2010.2097770
duction in NFmin of CMOS device along the scaling trend ,
 has imposed great challenges to noise de-embedding.
Several publications on noise de-embedding techniques,
which are based on the series-parallel equivalent-circuit model
– and generalized network model of test fixture –,
have been reported. The latter type of technique is well
known for its high generality and ability to account for the
transmission line effects of interconnects at high frequency.
However, the forward coupling mechanisms that exist on the
lossy substrate of the test fixture is not addressed in cascade
two-port-based techniques –. Meanwhile, high generality
of a four-port-based noise de-embedding technique , 
is compromised by ideality assumptions made on the intrinsic
standards of test structures. This results in accuracy degradation
of the de-embedding method at high frequency. On the other
hand, the complexity level of equivalent-circuit-model-based
techniques increases from – as accuracy at higher fre-
quency of characterization becomes critical. The more recent
technique  is superior to other methods, as it is able to re-
move parasitic effects of the test fixture for up to metal fingers
(Fig. 3). Therefore, it is increasingly important for transistor
characterization as the de-embedding reference plane is shifted
closer to the desired boundary of device. However, it ignores
the parasitic effects of probe to pad contact impedance and
could only de-embed for up to the Metal 2 level of the test
fixture. It is also associated with expensive implementation
cost and high de-embedding complexity, as it requires the same
number of test structures as  for the same purpose.
In this paper, a simple and accurate noise de-embedding
methodology is presented for noise characterization and mod-
eling of two-port transistor devices. It provides more accurate
prediction of the bond pad parasitic than other methods and
could de-embed test fixture parasitic for up to the Metal 1 level
while consuming 40% less silicon area than . In the proposed
de-embeddingtechnique, the test fixture parasitic is modeledby
generalized two-port networks to achieve high de-embedding
accuracy and alleviate the complexity of de-embedding due to
parasitic extraction. In particular, the proposed noise de-em-
bedding technique would be demonstrated on CMOS devices.
Such a noise de-embedding technique would be explained in
length in Section II. In Section III, the noise de-embedding
result is compared with other methods.
II. NOISE DE-EMBEDDING METHODOLOGY
In the proposed noise de-embedding technique, two port net-
works (Fig. 1),
andare used, respectively, to model
0018-9480/$26.00 © 2011 IEEE
480IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 59, NO. 2, FEBRUARY 2011
Fig. 1. Test fixture model of transistor test structure (DUT), which encom-
passes cascade parasitic networks ??
?? ?, and series parasitic network ?? ?. Note that DUT is the acronym for
?, parallel coupling network
Fig. 2. Schematic layout of ground shielded based transistor test structure
(DUT) in ground–signal–ground (G–S–G) configuration.
Fig. 3. De-embedding techniques that are proposed in , , and –
are designed to remove test fixture parasitics up to interconnect boundaries (Å )
only. The proposed technique, which is based on mix series-parallel configura-
tions of the parasitic, is able to establish de-embedding reference plane at the
Metal 1 level of metal fingers (B).
both series and parallel parasitic of interconnects plus metal fin-
andare not necessary to be reciprocal and
are valid regardless of circuit configuration of parasitic compo-
nents. The complicated steps in extraction of fixture parasitic
components are avoided as only two-port network parameters
and are needed to be known. Both cascading net-
and, represent the bond pad parasitics that
appear at Port 1 and Port 2, respectively. Instead of modeling it
Fig. 4. Types of dummy test structures that are adopted in proposed noise
de-embedding techniques: OPEN, SHORT, PAD SHORT-OPEN, and PAD
Fig. 5. Network/circuit models of dummy test structures that used for extrac-
tion of fixture parasitic. The circuit model of the PAD SHORT-OPEN structure
is identical to , with the exception that the bond pad parasitic components are
not assumed to be the same, which results in higher generality and accuracy.
with a single admittance element –, it is described by two
and pad to ground impedance
de-embedding technique differs from  in that the bond pad
parasitic elements of
identical. As a result, it could be applied to more general cir-
. The proposed noise
are not necessary to be
A. Test Structure
Fig. 2 illustrates the schematic layout of the ground shielded
based  transistor test structure that is used for characteri-
zation purposes. It consists of eight metal layers and is fabri-
cated on GLOBALFOUNDRIES’ 0.13- m CMOS technology.
The intrinsic nMOS device lies in the fixture gap of the Metal 1
ground shield and is surrounded by P
Metal 1 ground shield is set as the ground reference plane and
has a negligible resistance value . The enlarged view of an
nMOS device is shown in Fig. 3.
guard rings. The wide
LOO et al.: ACCURATE TWO-PORT DE-EMBEDDING TECHNIQUE 481
Fig. 6. Comparisons between measured (DUT) and de-embedded power gain ???
(b) and (c) Width ? ? ? ?? ?m, Length ? ???? ?m]at various dc-biasing conditions [(a) and (b) ?
frequency range from 4 to 80 GHz.
?? of transistor devices [(a) Width ? ? ? ? ?m, Length ? ???? ?m and
? ??? V and (c) ?
? ? V, ?
? ??? V] for
In order to minimize the parasitic effects of narrow intercon-
nects, broad signal pads are designed to allow probes moving
closer to the intrinsic nMOS device. Meanwhile, the width of
the signal pad is optimized to minimize the coupling between
pads. Edges on the interconnects and bond pads are chamfered
to minimize parasitic effects that are induced by step disconti-
Four types of dummy test structures (Fig. 4) are required for
characterization of fixture parasitic, namely, OPEN, SHORT,
PAD SHORT-OPEN, and PAD OPEN-SHORT. However, only
three dummy test structures are required for fabrication as
PAD OPEN-SHORT could be realized by simply rotating
PAD SHORT-OPEN 180 during on-wafer measurement. This
directly saves the cost of implementation while fulfilling the
requirement of proposed noise de-embedding technique. The
OPEN test structure is simply a fixture frame (without device)
that encompasses lead fingers at both the Metal 1 and Metal 2
level. The SHORT test structure is a similar version of OPEN
test structure with no fixture gap. The lead fingers are directly
connected to a highly conductive Metal1 ground shield through
Via1 without introducing additional connection parasitic, as
compared to . Also, the forward coupling effects on the
proposed SHORT structure can be neglected as there is no
fixture gap. With these layout configurations, the parasitic
effects of lead fingers can be effectively de-embedded up to the
Metal 1 level. Both the OPEN and SHORT structures that are
presented in  and  differs from the proposed technique
that the metal fingers are not included. On the other hand, both
PAD SHORT-OPEN and PAD OPEN-SHORT structure consist
of only bond pads, which are shorted by wide interconnects at
only one port than the other.
B. Characterization of Fixture Parasitic
The equivalent two-port network/circuit models of test struc-
tures are shown in Fig. 5. The model of the OPEN structure is
similar to the DUT test fixture model, but without the intrinsic
two-port device due to its layout configuration. On the other
hand, the parasitic effects of the Mp in SHORT structure is ig-
noredasthereis negligibleforward couplingeffect,whereasthe
interconnections. Bond pad parasitic elements that appear at
rameter measurements on both the PAD SHORT-OPEN struc-
ture and PAD OPEN-SHORT structure. The procedure for ex-
traction of the fixture parasitic is summarized as follows.
Step 1) Extract parasitic components of bond pad from mea-
and PAD OPEN-SHORT
is the system characteristic impedance.
Step 2) Determine two-port network parameters of series
parameters of SHORT structure
, is converted into the
. The obtained
are converted from their
Step 3) Extract two-port network parameters of parallel par-
eters of the OPEN structure
482IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 59, NO. 2, FEBRUARY 2011
Fig. 7. Comparisons between measured (DUT) and de-embedded noise parameters (NFmin, Rn, and Topt) of transistor devices [(a) and (b) Width ? ? ? ? ?m,
Length ? ???? ?m and (c) Width ? ? ? ?? ?m, Length ? ???? ?m] at various dc-biasing conditions [(a)–(d) ?
4 to 26 GHz. Note that the de-embedded noise parameters by proposed technique and other compared techniques – are almost identical in (c) and (d).
? ? ?? ? ??? V) for frequency range from
C. Procedure for-Parameter De-Embedding
The procedure for
Step 1) De-embed parasitic effects of
-parameter de-embedding is as follows:
parameters of transistor
. Convert the de-embedded result
Step 2) De-embed parasitic effects of
Step 3) De-embed parasitic effects of
and convert the
to the matrix,
D. Procedure for Noise De-Embedding
The procedure for noise de-embedding is as follows.
Step 1) Convert measured noise parameters (
matrix (in chain representation)
Step 2) Convert
de-embed parasitic noise effects of cascade compo-
) to the noise correlation
, , and by applying method
, and superscriptdenotes the
LOO et al.: ACCURATE TWO-PORT DE-EMBEDDING TECHNIQUE 483
Fig. 7. (Continued.) Comparisons between measured (DUT) and de-embedded noise parameters (NFmin, Rn, and Topt) of transistor devices [(e) and (f) Width ?
? ? ?? ?m, Length ? ???? ?m] at various dc-biasing conditions [(e) and (f) ?
de-embedded noise parameters by proposed technique and other compared techniques – are almost identical in (e) and (f).
? ? V, ?
? ??? V] for frequency range from 4 to 26 GHz. Note that the
Hermitian complex conjugate transpose
Step 3) De-embed parasitic noise effects of series network.
Step 4) De-embed parasitic noise effects of the parallel net-
Step 5) Lastly, convert
noise parameters of the intrinsic transistor device
to and calculate the
and) by applying the
III. DE-EMBEDDING VERIFICATION AND RESULTS
Noise measurements of 0.13- m nMOS devices are per-
formed by the ATN NP5B measurement system in conjunction
with HP8510C VNA for a frequency range from 4 to 26 GHz.
Measurements at frequency below 4 GHz are avoided as the
measured NFmin of the transistor approaches an uncertainty
limit of instrument , . Meanwhile, device characterization
at millimeter-wave frequencies ( 30 GHz) is performed by
an Agilent E8361A PNA (with a frequency extension module)
-parameter measurements. Additional OPEN and
SHORT structures of  and  (without metal fingers) are fab-
ricated for verification purposes. All test structures of –
are based on the same shielded pad frame as the proposed
structures for fair comparison of de-embedding techniques.
A. Impact of Fixture Parasitic on Transistor Power Gain
In this section, the performance of de-embedding techniques
at millimeter-wave frequencies is investigated on transistor
. Fig. 6(a) shows the measured and de-em-
bedded power gain of the nMOS device (Width
m) by various techniques at a dc bias of
and V. The difference between performance of
the proposed technique with and without considering parasitic
effects of probe to pad contact resistance is small (0.5 dB at
80 GHz) for frequencies below 80 GHz. This implies that
the large discrepancy between performance of the proposed
technique and  and  at high frequencies is mainly due to
parasitic effects of metal fingers (3 dB at 80 GHz).
On the other hand, de-embedding performance of the pro-
posed technique is identical to  when the probe to pad con-
tact resistance is neglected
slight improvement of transistor power gain over frequency is
observed (0.5 dB at 80 GHz) when the effect of probe to pad
contact resistance is taken into account by the proposed tech-
nique. This clearly demonstrates that the proposed technique is
more accurate than  at millimeter-wave frequencies.
In order to substantiate the verification results discussed
above, the de-embedded power gain of large width nMOS
devices at different dc-bias modes is also demonstrated.
Fig. 6(b) and (c) shows the measured and de-embedded
power gain of an nMOS device (Width
m) by various techniques at both triode
. In contrast, a
484IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 59, NO. 2, FEBRUARY 2011
Fig. 8. Results from reciprocity tests ??
Length ? ???? ?m] are passive at ?
Length ? ???? ?m and (d) Width ? ? ? ?? ?m, Length ? ???? ?m] for frequency range from 4 to 80 GHz at cutoff mode.
? confirm that both transistor devices [(a) Width ? ??? ?m, Length ? ???? ?m and (b) Width ? ???? ?m,
? ? ?? ? ? V. Comparisons between measured and de-embedded NFmin of transistor devices [(c) Width ? ? ? ? ?m,
techniques are consistent with those observed in Fig. 6(a)
for the device with a smaller width. However, the impact of
de-embedding is smaller for larger gain device due to domi-
nance of intrinsic transistor performance over the surrounding
test fixture parasitic. For example, the transistor power gain
performance shows improvement of only 3.2 dB at 80 GHz
after de-embedding by the proposed technique as compared to
11 dB for the device with a smaller width at the same dc-biasing
gain performance by the proposed technique and  are almost
identical ( 0.2-dB difference at 80 GHz) as the impact of con-
tact resistance becomes smaller for the transistor device with a
large size. Nevertheless, the results presented in Fig. 6(a)–(f)
confirms that the proposed de-embedding technique remains
valid regardless of transistor geometries.
V,V) and saturation regions (
V). The comparison results of de-embedding
V). Both de-embedded power
B. Comparison of Noise De-Embedding Results
The impact of de-embedding techniques on noise per-
formance of the nMOS device with different geometry is
also investigated. Fig. 7(a) and (b) shows the measured
and de-embedded noise parameters of transistor device
range from 4 to 26 GHz at the saturation mode (
V). As evidenced from the results presented in the
previous section, clear separation between the predicted NFmin
by the proposed technique and  and  beyond 15 GHz is
mainly contributed by parasitic effects of metal fingers. On the
other hand, de-embedded noise parameters by the proposed
technique are in good agreement with  for even a lesser
number of dummy test structures used. However, the distinc-
tion between de-embedded noise performance of the large size
transistor by the proposed technique and  and  remains
negligible for frequencies below 26 GHz at both saturation [see
Fig. 7(c) and (d)] and triode regions [see Fig. 7(e) and (f)].
Further, de-embedding by both the proposed technique and
compared techniques only resulted in a slight improvement of
the transistor NFmin by less than 1 dB at 26 GHz. These results
support the claim by  that nMOS devices with smaller
width or size are more vulnerable to de-embedding errors as
the transistor test structure (DUT) is increasingly dominated by
Direct noise measurement at millimeter-wave frequencies is
impossible due to the limitation of the existing noise measure-
ment system. Instead, the noise parameters of a transistor can
m, Length m) for a frequency
LOO et al.: ACCURATE TWO-PORT DE-EMBEDDING TECHNIQUE485
Fig. 9. (a) Comparisons between extracted gate capacitance of 0.13-?m nMOS devices by different de-embedding techniques at ?
parisons between bond pad parasitic elements at two-port ?? ??
(d) Residual error (expressed in percentage of device NFmin) in de-embedded NFmin of the nMOS device as a result of failure to account for the discrepancy
between bond pad parasitic elements at two ports. NF50 of input and output bond pad parasitic networks ??
from 4 to 80 GHz.
? ? ?? ? ? V. Com-
) and ?? ??
? [magnitude (b) and phase (c)] for frequency range from 4 to 80 GHz.
? are also shown for same frequency range
once it operates as a passive device. The equality between
and(both magnitude and phase) in Fig. 8(a) and (b) con-
firms that both of the transistor devices mentioned above are re-
ciprocal and passive at the cutoff mode (
Fig. 8(c) and (d) illustrates the comparisons between the ex-
tracted and de-embedded NFmin of the nMOS devices by var-
ious techniques for frequency from 4 to 80 GHz at zero gate
and drain bias. Both results presented in Fig. 8(c) and (d) show
posed technique and  and  increases consistently along the
frequency axis as the impact of metal finger parasitic becomes
impact on the transistor with smaller size (Width
m), as clearly shown by the 4-dB margin in
between the de-embedded NFmin by the proposed technique
and  and  at 80 GHz. Similar to the results presented in
Fig. 6(a)–(f), noise de-embedding performance of both the pro-
the same OPEN and SHORT structures used. The performance
of the five-step de-embedding technique would be worse than
predicted if it is based on the original proposed structures in 
(nonshielded based), which can de-embed t he fixture parasitic
for up to the Metal 2 level only.
C. Validation of Metal Finger Parasitic Effects
In order to verify the accuracy of the de-embedding tech-
niques, the total zero bias
pacitance of the 0.13- m nMOS device
a sufficiently low frequency (2 GHz) such that it could be ap-
ponents of the nMOS device are negligible since it is turned off
. The extracted gate capacitance after de-embedding is then
compared with the reference value that is calculated based on
process parameters of the 0.13- m CMOS technology. The re-
sults in Fig. 9(a) clearly show that the extracted gate capaci-
tance using the proposed technique and  are closely matched
withthe reference value.It varies proportionallywith thedevice
size as indicated (
of Device #1
#2). This confirms that the proposed technique could correctly
while, extracted gate capacitance of Device #1 by  and  is
V gate ca-
is extracted at
486IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 59, NO. 2, FEBRUARY 2011
about five times higher than actual value as the parasitic capac-
itance between metal fingers is included in the result.
D. Variability of Bond Pad Parasitic Elements
Variability between bond pad parasitic elements of
is also investigated and its impact on the noise de-em-
bedding result is discussed. In order to produce stable and con-
sistent results, the skating distances of probes are maintained
around 50 to 60 m . Fig. 9(b) and (c) shows the extracted
bond pad parasitic components of the test fixture, which include
probe to pad contact impedances
). Note that the impedance value of
has a magnitude of approximately 40% higher than
erage for frequency range from 4 to 80 GHz. This is mainly due
to the discrepancy in surface profiles of probes, which resulted
in a different contact area between the probe and bond pad .
In contrast, the difference between pad to ground admittances
is negligible even at 80 GHz. Variations between
bond parasitic elements at the input and output ports resulted
in increasing separation between NF50 of bond pad parasitic
and along the frequency domain [see
Fig. 9(d)]. Failure to account for such variation by  would in-
duce 3.9% to 6% error (at 80 GHz) in the de-embedded NFmin
of the transistor devices highlighted in Fig. 9(d). In other words,
more accurate prediction of the bond pad parasitic by the pro-
posed technique has led to better noise de-embedding perfor-
mance than other reported work –.
and pad to ground
In this paper, an accurate and simple noise de-embedding
methodology has been proposed for high-frequency noise char-
acterization of transistor devices. It is developed based on a
generalized two-port fixture model in conjunction with a set
of shielded-based test structures, which enable accurate de-em-
bedding of the test fixture parasitic for up to metal fingers. The
proposed noise de-embedding technique has been validated on
0.13- m technology based CMOS transistors for up to 80 GHz.
It shows superior performance to techniques  and  at high
frequencies as the parasitic effects of metal fingers dominate.
pability (for up to metal fingers), the proposed technique con-
sumes less silicon area, is simpler, and has been proven to be
more accurate in high-frequency characterization of the active
CMOS device. Further, better prediction of the bond pad par-
asitic gives additional boost to the noise de-embedding perfor-
mance of the proposed technique as compared to other reported
work –. These advantages confirmed that the proposed
CMOS devices at millimeter-wave frequencies. Moreover, the
proposed technique can also be applied to other types of active
devices, which include III–V compound transistors.
The authors are grateful to GLOBALFOUNDRIES Singa-
pore Pte Ltd., Singapore, for fabricating the test structures.
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Xi Sung Loo was born in Kuala Lumpur, Malaysia,
in 1982. He received the B.E. (Hons.) degree in elec-
nological University, Singapore, in 2007, and is cur-
rently working toward the Ph.D. degree at Nanyang
His research interests mainly focus on design,
layout optimization, and high-frequency noise
characterization of RF CMOS devices for modeling
LOO et al.: ACCURATE TWO-PORT DE-EMBEDDING TECHNIQUE487
Kiat Seng Yeo (SM’09) received the B.E. (Hons.)
degree in electronics and Ph.D. degree in electrical
Singapore, in 1993 and 1996, respectively.
In 1996, he joined the School of Electrical and
Electronic Engineering, Nanyang Technological
University, as a Lecturer, and became an Asso-
ciate Professor and Professor in 2002 and 2009,
respectively. He became Sub-Dean (Student Affairs)
in 2001, Head of the Department of Circuits and
Systems in 2005, and Interim Director, VIRTUS,
Integrated Circuit (IC) Design Centre of Excellence in 2009. He provides
consultancy services to statutory boards and multinational corporations in the
areas of semiconductor devices and electronic circuit design. He has been
extensively involved in the modeling and fabrication of small MOS/bipolar
integrated technologies for the last 17 years. His current research interests
include the design of new circuits and systems (based on scaled technologies)
for low-voltage low-power applications, RFIC design, integrated circuit design
ofBiCMOS/CMOS multiple-valuedlogiccircuits,domino logicandmemories,
and device characterization of deep-submicrometer MOSFETs.
Kok Wai J. Chew (M’02) received the B.E.
(Hons.) degree in electrical engineering and M.Eng.
and Ph.D. degrees in electrical engineering from
Nanyang Technological University, Singapore, in
1996, 1999, and 2007, respectively.
In 1998, he joined Chartered Semiconductor
Manufacturing, Singapore, as an Engineer with the
Mixed-Signal/RF CMOS Technology Development
Group, where he was involved in mixed-signal
process characterization and integration, RF CMOS
device layout, and characterization. In 2002, he
became a Senior Engineer and joined the SPICE Modeling Group, where he is
currently responsible for RF CMOS and SiGe BiCMOS actives and passives
test-chip design, characterization, modeling, and customer support across all
technologies. He is a Member of Technical Staff and Group Leader for RF
CMOS characterization and modeling. He has authored or coauthored over
15 papers in leading technical journals and conferences worldwide. He holds
18 U.S. patents. His research interests include characterization and modeling
of RF MOS/bipolar transistors, RF passives, and noise characterization and
modeling of MOS transistors.
Lye Hock Kelvin Chan was born in Penang,
Malaysia, in 1983. He received the B.E. (Hons.)
degree in electrical and electronic engineering from
Nanyang Technological University, Singapore, in
2007, and is currently working toward the Ph.D.
degree at Nanyang Technological University.
His research interests mainly focus on design and
high-frequency noise modeling of RF CMOS device
for low-power applications.
Shih Ni Ong was born in Johor, Malaysia, in 1983.
Shereceivedthe B.E. (Hons.)degreein electricaland
electronic engineering from Nanyang Technological
University, Singapore, in 2007, and is currently
working toward the Ph.D. degree at Nanyang Tech-
Her research interests mainly focus on high-fre-
quency noise characterization and modeling of RF
CMOS device for IC design purposes.
Manh Anh Do (SM’05) received the B.Sc degree
in physics from the University of Saigon, Saigon,
Vietnam, in 1969, and the B.E. (Hons.) degree in
from the University of Canterbury, Canterbury, New
Zealand, in 1973 and 1977, respectively.
From 1977 to 1989, he held various positions in-
cluding: Design Engineer, Production Manager, and
Research Scientist in New Zealand, and Senior Lec-
turer with National University of Singapore. In 1989,
he joined the School of Electrical and Electronic En-
gineering, Nanyang Technological University (NTU), Singapore, initially as a
Senior Lecturer, then an Associate Professor in 1996, and then Professor in
2001. He has been a consultant for many projects in the electronic industry, and
Pricing (ERP) Project in Singapore from 1990 to 2001. From 1995 to 2005, he
was Head of the Division of Circuits and Systems, NTU. He is currently the Di-
rector of the Centre for Integrated Circuits and Systems, NTU. He has authored
or coauthored over 100 papers in leading journals and 135 papers international
conferences in the areas of electronic circuits and systems. His current research
is focused on mobile communications, RF IC design, mixed-signal circuits and
intelligent transport systems. Prior to that, he specialized in sonar designing and
biomedical signal processing.
Dr. Do is a Fellow of the Institution of Engineering and Technology (IET),
U.K. He is a Chartered Engineer. He was a council member of the IET (from
2001 to 2004). He was an associate editor for the IEEE TRANSACTIONS ON
MICROWAVE THEORY AND TECHNIQUES (2005, 2006).
Chirn Chye Boon received the B.E. degree (Hons.)
in electronics and Ph.D. degree in electrical engi-
neering from Nanyang Technological University
(NTU), Singapore, in 2000 and 2004, respectively.
In 2005, he joined NTU, as a Research Fellow and
became an Assistant Professor that same year. Prior
to that, he was with Advanced RFIC, where he was a
Senior Engineer. He specializes in direct conversion
RF transceiver front-end design, phase-locked-loop
frequency synthesizers, clock and data recovery cir-
cuits, and frequency dividers.
Dr. Boon is a reviewer for the IEEE TRANSACTIONS OF CIRCUITS AND
SYSTEMS—PART I: REGULAR PAPERS, the IEEE MICROWAVE AND WIRELESS
COMPONENTSLETTERS, andthe IEEETRANSACTIONSONMICROWAVETHEORY