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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 46, NO. 2, FEBRUARY 2011485

Nanosecond Delay Floating High Voltage Level

Shifters in a 0.35 ?m HV-CMOS Technology

Yashodhan Moghe, Torsten Lehmann, Senior Member, IEEE, and Tim Piessens, Member, IEEE

Abstract—We present novelcircuits for high-voltage digital level

shifting with zero static power consumption. The conventional

topology is analysed, showing the strong dependence of speed and

dynamic power on circuit area. Novel techniques are shown to

circumvent this and speed up the operation of the conventional

level-shifter architecture by a factor of 5–10 typically and 30–190

in the worst case. In addition, these circuits use 50% less silicon

area and exhibit a factor of 20–80 lower dynamic power consump-

tion typically. Design guidelines and equations are given to make

the design robust over process corners, ensuring good production

yield. The circuits were fabricated in a 0.35

CMOS process and verified. Due to power and IO speed limitation

on the test chip, a special ring oscillator and divider structure was

used to measure inherent circuit speed.

m high-voltage

Index Terms—CMOS, DMOS, fast, floating, high speed, high

voltage, high-speed, high-voltage, HV, HV CMOS, HV-CMOS,

HVCMOS, level shifter, level-shifter, low power, low-power, re-

duced area, ultra fast, ultra-fast.

I. INTRODUCTION

M

(hereafter simply referred to as DMOS) transistors and N-wells

that can float up to high voltages above the chip substrate. It is

common practice to place low voltage (LV) circuitry in these

floating wells and communicate between the various voltage

domains via DMOS cascodes, particularly for digital control

signals. Various techniques have been described in the literature

[1]–[12]. While these designs are useful for their applications,

they have disadvantages, as shown in Table II:

1) Low switching speed [1], [2]: This is due to the high gate

and drain capacitances of DMOS transistors or the delay

through a LV transistor stack

2) Large silicon area [1], [2], : This is due to the inability to

share floating N-wells among PDMOS transistors or the

large area of a LV transistor stack

ODERN CMOS triple-well processes offer HV ex-

tensions via special DMOS or drain-extended MOS

Manuscript received April 23, 2010; revised August 08, 2010; accepted Oc-

tober 12, 2010. Date of publication December 10, 2010; date of current version

January 28, 2011. This paper was approved by Associate Editor Philip K. T.

Mok. This work was supported by Cochlear Ltd.

Y.MogheiswiththeSilannaGroup,SydneyOlympicPark,Australia(e-mail:

yash.moghe@silanna.com).

T. Lehmann is with the School of Electrical Engineering and Telecom-

munications, University of New South Wales, Sydney, Australia (e-mail:

tlehmann@unsw.edu.au).

T. Piessens is with ICsense, B-3001 Leuven, Belgium (e-mail: tim.

piessens@icsense.com).

Color versions of one or more of the figures in this paper are available online

at http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/JSSC.2010.2091322

TABLE I

SIMULATED AND MEASURED RESULTS

3) Staticpowerconsumption[3]–[9]:Notsuitableforbattery-

powered (especially implantable) applications

4) Dynamic control signals [4], [10]: This increases system

complexity, especially for arrays of level shifters

5) High voltage capacitors [11], [12]: In many processes, HV

capacitors can be constructed only with normal routing

metals(overlaporfingerarrangement),requiringlargearea

to obtain reasonable capacitance values

The novel techniques in this paper avoid the above draw-

backs while simultaneously improving silicon area, speed and

dynamic power consumption. The techniques described are ad-

ditive, in that they build on each other, resulting in a perfor-

manceincreaseeachtime.Wefocusonimplementationsthatre-

quire only thin-oxide DMOS transistors (high drain-source and

drain-gatevoltagebutlowgate-sourcevoltage)astheseworkef-

ficiently over a wide range of supply voltages; and furthermore,

thick-oxide DMOS transistors are not always available. Never-

theless, many of these techniques are generic and easily ported

to thick-oxide DMOS designs.

These techniques are robustand specifically account for wide

process variations (process corners), ensuring high production

yield. The circuits, along with special test circuitry, were fabri-

cated on a 0.35 m HV CMOS process and tested.

II. CONVENTIONAL HV LEVEL SHIFTING

While many variations on HV level shifting circuits exist

in the literature, we focus on those that draw no static supply

current and don’t require HV capacitors. The classic design

transforms the well-known low voltage level shifter [Fig. 1(a)]

to a HV equivalent using DMOS cascodes [2] [Fig. 1(b)]. In

0018-9200/$26.00 © 2010 IEEE

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486 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 46, NO. 2, FEBRUARY 2011

TABLE II

COMPARISON WITH PREVIOUS WORK BY OTHERS

Fig. 1. Basic level shifting: (a) low-voltage prototype; (b) transformed to HV; (c) with simple modifications. Device dimensions given in microns. Dashed boxes

indicate separate N-wells. All devices are placed in N-wells. nMOS transistors are placed in P-wells inside N-wells (not directly in the P-substrate).

Fig. 1(b), the NDMOS cascode transistors M1/M2 (with gates

connected to

) protect the LV pull-down transistors. Sim-

ilarly, the PDMOS transistors M3/M4 (with gates connected to

) protect the floating LV circuitry sitting between the

andrails. Dashed boxes indicate separate N-wells. On

mostHVCMOSprocesses,NDMOStransistorsmusteachhave

their own N-well (the drain terminal).

Even for this basic circuit, improvements can be made as

shown in Fig. 1(c). The NDMOS transistors are used directly as

pull-downs rather than as cascodes, saving some area. Two ad-

ditionallow-voltagenMOStransistorsM7/M8are alsoaddedto

the floating circuitry to prevent the sources of the PDMOS tran-

sistors being pulled more than a diode drop below

wise, even though a PDMOS transistor may be off, leakage can

pull its source down by several volts, weakening or destroying

the gate oxide. Khorasani et al. [9] used resistor pull-ups to

achievethesame effect,butwiththedisadvantageofdissipating

static power.

. Other-

A. Device Sizing for DC Operation

In this section, we derive design equations for DC operation

for the LV and HV circuits in Fig. 1 to show the difficulty in the

LV-to-HV transformation. To explicitly avoid negative quanti-

ties in the algebra, we use the symbols

N-channel and P-channel threshold voltages respectively. Fur-

thermore, for brevity we use

cating N-channel or P-channel.

For theLV prototype in Fig.1(a), consider the case where

is high. In this state, the gates of M1 and M3 are both at

flip the state of the level shifter, M1 needs to be sized relative

to M3 such that when the gate of M1 is set to

gate of M3 is still at

, the common drain voltage

pulleddowntoatleast

below

state cannot be flipped quickly. By symmetry, M2 and M4 are

sized the same way. Under these conditions, M1 is in the active

region(assumingsimilarthresholdvoltagesforPandNchannel

transistors and

), while M3 is in the triode region.

We assume M3 is in the linear triode region to conservatively

overestimate its strength.

The currents through M1 and M3 are given by:

and to denote

, with a subscript indi-

. To

and the

can be

–otherwisethelatched

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MOGHE et al.: NANOSECOND DELAY FLOATING HIGH VOLTAGE LEVEL SHIFTERS IN A 0.35m HV-CMOS TECHNOLOGY 487

Since M1 and M3 pass the same current, we equate the two

equations to derive the following design equation:

(1)

For good yield, the NMOS/PMOS ratio is set for the slow

N/fast P corner with maximum

FortheHVtransformedcaseinFig.1(c),thesituationisquite

different. As M1 turns on,

is pulled down, and since M3 is

on,

follows. However, as

creases, making the pulldown weaker. Therefore, it can be seen

thattheratioofM3toM5isthecriticaldesignparameter.Again,

M2, M4 and M6 are sized to make the circuit symmetrical. In

the following equations, we set

braic brevity and solve for the case where

As for the LV case, M5 is conservatively taken to be in the

linear triode region and the current through it is given by

and minimum.

drops, the gate drive on M3 de-

for alge-

.

If, which is easily achieved with a minimum size

M1, then M3 is in the active region with current:

where the additional subscript

Equating

and

is used to indicate DMOS.

gives the following design equation:

(2)

Firstly, from the denominator of (2), the floating voltage do-

main

must be greater than

erwise, M3 works in the subthreshold region during pulldown,

which makes for a very large ratio in (2). In simulation with

equal to 1.4 V (approximately two threshold volt-

ages), device ratios in excess of 100 were required for correct

DC operation of the level shifter, confirming the above calcula-

tion. Secondly, for good production yield, the sizing should be

done for the slow P corner (strong/weak N is irrelevant here, but

relevant in later sections).

The difficulty in going from the LV case to the HV case is

apparent when the sizing ratios in (1) and (2) are evaluated. For

designpurposes,

(approximately three threshold voltages), and all device dimen-

sions given in this paper are for these conditions. For many 0.35

m CMOS processes (including this one), the ratio

nominally equal to 1/3, mainly due to the ratio of hole to elec-

tron mobility, but in the fast P/slow N corner this increases to

1/2. In the fast P/slow N corner, the values for

are approximately equal to 0.5 V and 0.7 V respectively for this

process.Undertheseconditions,(1)dictatesadevicesizingratio

.

For the HV case, the critical device sizing ratio is much

higher. In general,

and

slow P corner are both approximately equal to 0.8 V for this

process. The ratio

for most HV processes typically

ranges from 2 to 5 and this is set by the tradeoff between

. Oth-

wasused

is

and

track each other, and in the

on-resistance and breakdown voltage for DMOS transistors.

The DMOS transistors we used had a breakdown voltage of

14 V, with a

ratio of 2. Under these conditions, (2)

dictates a device sizing ratio

M3/M5. This corresponds to the dimensions in this paper. In

simulation in the slow P corner, we found that DC operation

of the circuit was compromised below

which confirms the above calculation.

M1 is also scaled relative to M5 according to the following

equation (which is very similar to (1)):

for

,

(3)

Again,thescalingisdonefortheslowN/fastPcorner.Forthe

technology we used, the ratio

was equal to 0.75. Note that this is higher than the case for

the LV level shifter due to the lower ratio of

NDMOS case. As shown in the next section, a minimum sized

M1 is more than sufficient.

for M1/M5

for the

B. Dynamic Performance Calculations

The delay through the basic HV level shifter is composed of

the transient behaviour on the four circuit nodes

andshown in Fig. 1(c). Fig. 2 shows a top view and wafer

cross section of the devices M1, M3, and M5. The various gate

andjunctioncapacitancesareshown,toaidinunderstandingthe

transient behaviour of the circuit. The diagram is not to scale.

Consider the case when

level shifter, the following sequence takes place:

1)

goes high, charging up the gate capacitance

of M1. The inverter I1 similarly discharges the gate capac-

itance of M2

2) The node

begins to drop rapidly as shown in Fig. 4.

Nodes

andhave the largest parasitic capacitance,

as explained below, however M1 is switched on very

strongly in the active region and discharges the capaci-

tanceon

quickly.Thenode

statebutremainssteadyduetothecapacitanceonthenode.

3) Node

quickly follows

voltage at least

below

relative sizing of M3 and M5. We denote the time delay

thus far

. At this time, the node

large step increase.

4) Node

charges up to the same voltage as

denote this time delay

5) Node charges up slowly and linearly as shown in

Fig.4 due tothecombination of largeparasitic capacitance

and low current through the weakly switched on devices

M4 and M6 that are both in the active region. We denote

this time delay

6) Oncechargesuptothesamevoltageas

charge up towards the

drops further down and the positive transition on

completes. We denote this time delay

The total delay through the level shifter is composed of the

sum

. is quite small because although the

parasiticcapacitance onnode

,,

is initially low. To switch the

isinahigh-impedance

down until it reaches a

, as determined by the

experiences a

and we

,theyboth

rail. As this happens, node

.

is large,thepulldownstrength

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488IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 46, NO. 2, FEBRUARY 2011

Fig. 2. Top view and cross section of important devices in basic HV level-shifter with critical dimensions marked. Diagram not to scale.

Fig. 3. Equivalentcircuitduring time? . Dashedline indicates virtualconnec-

tion.

of M1 and M3 is high, resulting in a fast transient.

small because the required voltage swing on node

and can be accomplished quickly.

nation of high parasitic capacitance on node

pullup capability of M6.

only able to pull

quickly to within a threshold voltage of

. Thereafter, only subthreshold current can discharge the

node further.

,,,are shown in Fig. 4.

We now give a derivation of the

changeswithdevicewidthandthevaluesof

do not give a derivation of

since we show later in Section III

how to minimise it by various techniques.

is also

is small

is large due to the combi-

and the low

can also be large because M3 is

parameter to show how it

and .We

is the time that it takes node

above

– that is, nearly through the entire

During this time, nodes

cuitsymmetry. M6 thusacts likea diode-connected transistorin

the active region. M4 is also in the active region. The currents

through M4 and M6 are given by

to charge fromto

voltage.

andare equal by reason of cir-

(4)

(5)

For algebraic simplicity,

and

to be the local ground potential and specify

voltages relative to that. Equating currents through M4 and M6

gives

we makethesubstitution

. That is, we

consider

(6)

However, from (2), we know

where

ages for pMOS and PDMOS respectively in the slow P process

corner. Also, as explained earlier,

(PMOS and PDMOS transistors track each other

across process corners) and

tuting these into (6) and solving for

andrepresent the threshold volt-

and

. Substi-

, we get

(7)

Substituting this back into (4) gives

(8)

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MOGHE et al.: NANOSECOND DELAY FLOATING HIGH VOLTAGE LEVEL SHIFTERS IN A 0.35m HV-CMOS TECHNOLOGY 489

Fig. 4. Transient operation of basic HV level shifter. Delays ? -? (Section II-B) indicated.

To understand the speed at which node

examine the dynamic circuit consisting of ideal transistors and

major parasitic capacitances shown in Fig. 3. The dashed line

shows the virtual diode connection of M6. In reality, the in-

stantaneous currents through M4 and M6 are not the same due

to the presence of

. The current required to discharge

during the transient actually flows through M4, thus

increasingthe

voltageandmakingthevirtualdiodeconnec-

tion of M6 not strictly valid. However, we verified in simulation

that the error in current associated with making the diode con-

nection assumption is less than 10%, and is thus acceptable in

order to simplify the analysis.

Node

is a low-impedance node due to the virtual diode

connection assumption, and hence

part in the dynamic response. Capacitances

andexperience the same voltage change at node

which needs to be supplied by the current

From Fig. 2, the value of

charges up, we

andplay no

,

,

in (8).

is given by

where

the P-well/N-well interface and

mension

width beyond the NDMOS width).

is always chosen to be minimum.

depths of P-wells and N-wells respectively. Therefore,

can be rewritten as

is the junction capacitance per square micron of

is the constant di-

(twice the overhang of the P-well

is constant since

and are the

(9)

where

and are constants defined as

Similarly, andcan be written as

(10)

(11)

where the constants are similarly defined as:

The total capacitance is the sum of the three above:

(12)