Nanosecond Delay Floating High Voltage Level Shifters in a 0.35 mu m HV-CMOS Technology

Silanna Group, Sydney, NSW, Australia
IEEE Journal of Solid-State Circuits (Impact Factor: 3.01). 03/2011; 46(2):485 - 497. DOI: 10.1109/JSSC.2010.2091322
Source: IEEE Xplore


We present novel circuits for high-voltage digital level shifting with zero static power consumption. The conventional topology is analysed, showing the strong dependence of speed and dynamic power on circuit area. Novel techniques are shown to circumvent this and speed up the operation of the conventional level-shifter architecture by a factor of 5-10 typically and 30-190 in the worst case. In addition, these circuits use 50% less silicon area and exhibit a factor of 20-80 lower dynamic power consumption typically. Design guidelines and equations are given to make the design robust over process corners, ensuring good production yield. The circuits were fabricated in a 0.35 high-voltage CMOS process and verified. Due to power and IO speed limitation on the test chip, a special ring oscillator and divider structure was used to measure inherent circuit speed.

Full-text preview

Available from:
  • Source
    • "Level shifter is used in multi supply voltage systems where voltage difference problem exist. Level shifters are used in aero space systems, MEMS, power converters, and in microprocessors [12]-[21]. "
    [Show abstract] [Hide abstract]
    ABSTRACT: The level converter is used as interface between low voltages to high voltage boundary. The efficient level converter has less power consumption and less delay are the design considerations of the level shifter. In this paper two new CMOS level converters are presented with high driving capability and low propagation delay. The proposed level converters are simulated using Cadence software with 0.18 µm CMOS technology. The simulation result shows that the proposed circuits have less propagation delay than existing ones. The circuits are simulated with different load capacitor values and different voltages. The proposed level converters operate for different input pulse signal amplitude values are +0.8 V, +1 V, +1.2 V and VDDH values of +1.8 V and +3.3 V.
    09/2014; 3(2):44-52. DOI:10.11601/ijates.v3i2.92
  • [Show abstract] [Hide abstract]
    ABSTRACT: A level shifter circuit capable of extremely low- voltage inputs is presented in this paper. The circuit has a distinctive feature in current generation scheme with logic error correction circuit by detecting input and output logic levels. The proposed circuit can convert low-voltage input digital signals into high-voltage output digital signals. The circuit achieves low- power operation because it dissipates operating current only when the input signals change. Measurement results demon- strated that the circuit can convert low-voltage input signals of 0.4 V into 3 V output signals. The power dissipation was 58 nW at 0.4-V and 10-kHz input pulse.
    Proceedings of the 37th European Solid-State Circuits Conference, ESSCIRC 2011, Helsinki, Finland, Sept. 12-16, 2011; 01/2011
  • [Show abstract] [Hide abstract]
    ABSTRACT: Keeping power consumption low in implantable neuro-stimulators such as Cochlear Implants or Vision Prostheses is one of the major design challenges in their circuit design. Usually electrode impedance and stimulation currents required to elicit physiological responses mandates the use of large stimulation voltages, again dictating the use of high-voltage integrated circuit technologies. Power consumption in the stimulating circuits and associated supply generation circuits are the major contributors to overall system power dissipation. In this paper we present circuit design techniques that address power consumption in both stimulating circuits and power supply circuits. First, our stimulating circuits design approach is to use very small quiescent currents, fast turn-on time and pre-stimulating dynamic calibration which allow the delivery of charge balanced bi-phasic stimulation pulses with very good power efficiency. Second, our power supply design approach is to recycle currents between the two low-voltage power supply needed for the stimulating circuits, whereby power consumption in these circuits can be close to halved. In combination, significant implant power consumption reduction is achieved.
    Midwest Symposium on Circuits and Systems 01/2011; 21(06):1-4. DOI:10.1109/MWSCAS.2011.6026470
Show more