IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 46, NO. 2, FEBRUARY 2011485
Nanosecond Delay Floating High Voltage Level
Shifters in a 0.35 ?m HV-CMOS Technology
Yashodhan Moghe, Torsten Lehmann, Senior Member, IEEE, and Tim Piessens, Member, IEEE
Abstract—We present novelcircuits for high-voltage digital level
shifting with zero static power consumption. The conventional
topology is analysed, showing the strong dependence of speed and
dynamic power on circuit area. Novel techniques are shown to
circumvent this and speed up the operation of the conventional
level-shifter architecture by a factor of 5–10 typically and 30–190
in the worst case. In addition, these circuits use 50% less silicon
area and exhibit a factor of 20–80 lower dynamic power consump-
tion typically. Design guidelines and equations are given to make
the design robust over process corners, ensuring good production
yield. The circuits were fabricated in a 0.35
CMOS process and verified. Due to power and IO speed limitation
on the test chip, a special ring oscillator and divider structure was
used to measure inherent circuit speed.
Index Terms—CMOS, DMOS, fast, floating, high speed, high
voltage, high-speed, high-voltage, HV, HV CMOS, HV-CMOS,
HVCMOS, level shifter, level-shifter, low power, low-power, re-
duced area, ultra fast, ultra-fast.
(hereafter simply referred to as DMOS) transistors and N-wells
that can float up to high voltages above the chip substrate. It is
common practice to place low voltage (LV) circuitry in these
floating wells and communicate between the various voltage
domains via DMOS cascodes, particularly for digital control
signals. Various techniques have been described in the literature
–. While these designs are useful for their applications,
they have disadvantages, as shown in Table II:
1) Low switching speed , : This is due to the high gate
and drain capacitances of DMOS transistors or the delay
through a LV transistor stack
2) Large silicon area , , : This is due to the inability to
share floating N-wells among PDMOS transistors or the
large area of a LV transistor stack
ODERN CMOS triple-well processes offer HV ex-
tensions via special DMOS or drain-extended MOS
Manuscript received April 23, 2010; revised August 08, 2010; accepted Oc-
tober 12, 2010. Date of publication December 10, 2010; date of current version
January 28, 2011. This paper was approved by Associate Editor Philip K. T.
Mok. This work was supported by Cochlear Ltd.
T. Lehmann is with the School of Electrical Engineering and Telecom-
munications, University of New South Wales, Sydney, Australia (e-mail:
T. Piessens is with ICsense, B-3001 Leuven, Belgium (e-mail: tim.
Color versions of one or more of the figures in this paper are available online
Digital Object Identifier 10.1109/JSSC.2010.2091322
SIMULATED AND MEASURED RESULTS
powered (especially implantable) applications
4) Dynamic control signals , : This increases system
complexity, especially for arrays of level shifters
5) High voltage capacitors , : In many processes, HV
capacitors can be constructed only with normal routing
to obtain reasonable capacitance values
The novel techniques in this paper avoid the above draw-
backs while simultaneously improving silicon area, speed and
dynamic power consumption. The techniques described are ad-
ditive, in that they build on each other, resulting in a perfor-
quire only thin-oxide DMOS transistors (high drain-source and
ficiently over a wide range of supply voltages; and furthermore,
thick-oxide DMOS transistors are not always available. Never-
theless, many of these techniques are generic and easily ported
to thick-oxide DMOS designs.
These techniques are robustand specifically account for wide
process variations (process corners), ensuring high production
yield. The circuits, along with special test circuitry, were fabri-
cated on a 0.35 m HV CMOS process and tested.
II. CONVENTIONAL HV LEVEL SHIFTING
While many variations on HV level shifting circuits exist
in the literature, we focus on those that draw no static supply
current and don’t require HV capacitors. The classic design
transforms the well-known low voltage level shifter [Fig. 1(a)]
to a HV equivalent using DMOS cascodes  [Fig. 1(b)]. In
0018-9200/$26.00 © 2010 IEEE
486 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 46, NO. 2, FEBRUARY 2011
COMPARISON WITH PREVIOUS WORK BY OTHERS
Fig. 1. Basic level shifting: (a) low-voltage prototype; (b) transformed to HV; (c) with simple modifications. Device dimensions given in microns. Dashed boxes
indicate separate N-wells. All devices are placed in N-wells. nMOS transistors are placed in P-wells inside N-wells (not directly in the P-substrate).
Fig. 1(b), the NDMOS cascode transistors M1/M2 (with gates
) protect the LV pull-down transistors. Sim-
ilarly, the PDMOS transistors M3/M4 (with gates connected to
) protect the floating LV circuitry sitting between the
andrails. Dashed boxes indicate separate N-wells. On
their own N-well (the drain terminal).
Even for this basic circuit, improvements can be made as
shown in Fig. 1(c). The NDMOS transistors are used directly as
pull-downs rather than as cascodes, saving some area. Two ad-
the floating circuitry to prevent the sources of the PDMOS tran-
sistors being pulled more than a diode drop below
wise, even though a PDMOS transistor may be off, leakage can
pull its source down by several volts, weakening or destroying
the gate oxide. Khorasani et al.  used resistor pull-ups to
A. Device Sizing for DC Operation
In this section, we derive design equations for DC operation
for the LV and HV circuits in Fig. 1 to show the difficulty in the
LV-to-HV transformation. To explicitly avoid negative quanti-
ties in the algebra, we use the symbols
N-channel and P-channel threshold voltages respectively. Fur-
thermore, for brevity we use
cating N-channel or P-channel.
For theLV prototype in Fig.1(a), consider the case where
is high. In this state, the gates of M1 and M3 are both at
flip the state of the level shifter, M1 needs to be sized relative
to M3 such that when the gate of M1 is set to
gate of M3 is still at
, the common drain voltage
state cannot be flipped quickly. By symmetry, M2 and M4 are
sized the same way. Under these conditions, M1 is in the active
), while M3 is in the triode region.
We assume M3 is in the linear triode region to conservatively
overestimate its strength.
The currents through M1 and M3 are given by:
and to denote
, with a subscript indi-
496 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 46, NO. 2, FEBRUARY 2011
An oscilloscope capture of the operation of the ring oscillator
and divider is shown in Fig. 14. The top trace shows the di-
vider output. The positive edge of the pulse on the bottom trace
switches the HV level shifters in the ring oscillator from the fast
mode to the ultra-fast mode.
Table II shows a comparison of this work to other previous
work. Where available, the technology node
of the level shifter has been recorded, and combined
into a figure of merit
the better. Prior works that equal or better the figure of merit of
this work all exhibit static power consumption and/or make use
of HV capacitors. As stated earlier, it was a design goal of this
work to avoid both of these.
– the lower the figure of merit
We presented a comprehensive analysis of the conventional
techniques for simultaneously improving switching speed, sil-
icon area and power consumption as well as eliminating the
asymmetrical switching characteristic. These techniques are ro-
bust to process variations and have been verified on silicon.
In Table I, it can be seen that for high
(2.5 V), the delay through the ultra-fast level
shifter increases by a factor of 10 typically and 190 in the worst
case corner compared to the basic level-shifter. Under the same
are reduced by factors of 20 and 180 respectively. For a higher
(3.3 V), the speed increase is lower but
still significant, being a factor of 5 typically and 30 in the worst
case corner. However, the improvement in dynamic power con-
sumption is much higher, being a factor of 80 typically and 720
in the worst case. Silicon area is reduced by 50% overall. Static
power consumption is eliminated and no HV capacitors are re-
so in battery powered and implantable applications.
(10 V) and low
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Yashodhan Moghe received the Bachelors degree
in electrical engineering and the Masters degree in
biomedical engineering from the University of New
South Wales (UNSW), Sydney, Australia, in 2001.
and then Senior Analog ASIC Designer at Cochlear
Ltd., Lane Cove, Australia, where he worked on
low-power analog and mixed-signal designs, in-
cluding the world’s first totally implantable cochlear
implant. He is currently Design Manager at Silanna
Group, Sydney Olympic Park, Australia, where
he works on various commercial and research-based design and technology
projects on Silicon-on-Sapphire (SoS) technology.
In 2006 he started a part-time Ph.D. in microelectronics at UNSW. His Ph.D.
research, for which he holds a patent, focuses on novel circuits and systems
to improve the electrical safety of multi-channel neurostimulator implants. His
Ph.D. work is funded by Cochlear.
Torsten Lehmann (SM’06) received the M.Sc.
and Ph.D. degrees in electrical engineering from
the Technical University of Denmark, Lyngby,
Denmark, in 1991 and 1995, respectively, for work
on self-learning VLSI neural networks.
the European Union at the University of Edinburgh,
Scotland, U.K., where he worked with biologically
he was an Assistant Professor in electronics at the
TechnicalUniversity of Denmark, workingwith low-
power low-noise low-voltage analog and mixed analog-digital integrated cir-
cuits. He worked briefly as an ASIC design engineer with Microtronics A/S,
Denmark. From 2001 to 2003 he was Principal Engineer with Cochlear Ltd.,
Australia, where he was involved in the design of the world’s first fully im-
plantable cochlear implant. Currently, he is a Senior Lecturer in microelec-
tronics at the University of New South Wales, Sydney, Australia. His main
research interests are in solid-state circuits and systems (analog and digital),
biomedical electronics and ultra-low-temperature electronics.
MOGHE et al.: NANOSECOND DELAY FLOATING HIGH VOLTAGE LEVEL SHIFTERS IN A 0.35m HV-CMOS TECHNOLOGY497
Tim Piessens was born in Bornem, Belgium, in
1975. He received the Masters degree in electrical
engineering and the Ph.D. degree in electronics from
the Katholieke Universiteit Leuven (K. U. Leuven),
Heverlee, Belgium, in 1998 and 2003, respectively.
From 1998 to 2003, he worked as a Research
Assistant at the ESAT-MICAS Laboratory, K. U.
Leuven, on the development of highly efficient line
drivers for xDSL systems. In 2004, he co-founded
the company ICsense, which is a fabless microelec-
tronics company specializing in integrated sensor