Conference Paper

Thermal-aware reliability analysis of nanometer designs

Adv. Micro Devices Inc., Sunnyvale, CA, USA
DOI: 10.1109/EPEPS.2010.5642793 Conference: Electrical Performance of Electronic Packaging and Systems (EPEPS), 2010 IEEE 19th Conference on
Source: IEEE Xplore

ABSTRACT Increasing current densities in deep sub-micron designs necessitate accurate power and thermal analysis to help verify compliance with chip-level reliability specifications. This paper presents a thermal-aware analysis flow that accurately captures the effects of design topology, currents, and switching constraints. This static analysis flow demonstrates the need to compute temperature at the level of interconnect metal, via resistors and device fingers, and was used to verify reliability constraints on successive iterations of nanometer-level designs.

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    ABSTRACT: A model for predicting Al interconnect and intermetallic contact/via electromigration time-to-failure under arbitrary current waveform is incorporated in a circuit electromigration reliability simulator. The simulator can (1) generate layout advisory for width and length of each interconnect, and the number of contacts and vias at each node in a circuit, and (2) estimate the overall circuit electromigration failure rate and/or cumulative percent failure as functions of time, temperature, voltage, frequency, and previous stress (e.g., burn-in)
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