Page 1
ThermalAware Relia
Srini Krishnamoorthy 
Thomas B
Srini.krishnamoorthy@amd.com
tom.bu
Advanced M
Tel: 1
ABSTRACT
Increasing current densities in deep sub
necessitate accurate power and thermal analys
compliance with chiplevel reliability specifica
presents a thermalaware analysis flow that ac
the effects of design topology, currents, and swit
This static analysis flow demonstrates the n
temperature at the level of interconnect metal,
device fingers, and was used to verify reliabil
successive iterations of nanometerlevel designs.
Keywords
Thermal Analysis, Reliability, Electromigration
1. INTRODUCTION
In deep submicron designs, metal interconnec
subject to everincreasing current densities and
wear out over time, causing chiplevel failures.
fail over time due to electromigration (EM) [11,
movement of metal atoms under high curr
gradients. Such failure mechanisms are exac
heating, which reduces mean time to fail
interconnects and places constraints on the avera
mean square (RMS) current density that an inte
support.
Accurately solving for currents in each intercon
circuit simulation [1,2,3] is a very computei
large designs. Previous work has demonstrated
analysis approach makes this a tractable pro
produces results within acceptable error bo
approaches [3,4] have also attempted to reduce
the analysis by filtering from the analysis nets
capacitance loads [3,4]. In deep submicron desi
everincreasing component density can cause the
induce failures in unsuspecting nets adjacent to h
Traditional process design manuals specify
interconnect DC and RMS current densities.
limits have become woefully inadequate for de
designs, and continue to worsen in each su
generation due to increasing power densities a
Approaches to thermal modeling for intercon
3D/2D finite element methods [7] to 1D heat d
[8,9]. The 1D approach offers a comprom
accuracy of finite element methods and th
calculating interconnect selfheating on a seg
basis, while ignoring the effects of heat diffusio
However, neighboring metal layers have been
temperature of interconnects carrying high cu
1
ability Analysis of Nanomet
 IEEE member, Vishak Venkatraman, Yuri Apa
Burd  Senior IEEE member, Anand Daga
m, Vishak.venkatraman@amd.com, yuri.apanov
urd@amd.com, anand.daga@amd.com
Micro Devices Inc., One AMD Place Sunnyvale
4087494000 Fax: 14087747811
bmicron designs
sis to help verify
ations. This paper
ccurately captures
tching constraints.
need to compute
via resistors and
lity constraints on
.
cts and transistors
d temperature can
Interconnects can
13], caused by the
rent and thermal
cerbated by Joule
lure (MTTF) of
age (DC) and root
erconnect line can
nnect segment via
intensive task for
that a static linear
oblem [4,5], and
ounds [5]. Other
the complexity of
s that drive small
igns, however, the
ermal gradients to
highcurrent nets.
fixed limits for
. However, these
eep submicron IC
uccessive process
and temperatures.
nnect range from
diffusion methods
mise between the
he simplicity of
gmentbysegment
on (0D approach).
n found to reduce
urrents [10]. Most
metal structures in deep submicron de
need to be modeled as such.
This paper presents a static analysis flo
temperature at interconnect resistor
current computation step uses an impe
a subtle difference over previous static
accurately models current steering
charge/discharge paths encountered in
computed currents are then used to co
the design elements. The total desi
computed by accounting for switchin
hot, in which only a single net out of a
any given time. The 3D thermal analy
accurately captures the thermal diffus
multilayered interconnects, and diel
using the design power numbers updat
constraints. This work shows power an
at the resistor and transistor level is ex
EM and TDDB verification.
2. ANALYSIS OVERVIEW
Figure 1 presents a general diagram o
targets fullcustom designs. With min
approach can be applied to stdcell b
inputs to the tool include design data s
views (transistor netlists); a parasiti
annotated with physical layer informa
properties such as edge rate, switchi
load on the design ports; design layou
file describing processspecific parame
Figure 1. Proposed Stat
Based on the topological connectivity
supplies specified in the techfile, the
channelconnected regions (CCRs)
governing each CCR, along with swit
ter Designs
novich,
vich@amd.com,
CA 94088
esigns are highdensity, and
ow that computes power and
and transistor levels. The
edancebased analysis, with
c approaches in that it more
among multiple parallel
custom circuit designs. The
ompute power dissipated by
gn power is subsequently
ng constraints such as one
a collection of nets is high at
ysis discussed in this paper
sion through the transistors,
lectric stack in the design
ted to account for switching
nd temperature computation
xtremely important to design
W
of our analysis flow, which
nor modifications, the same
based designs as well. The
such as logical and physical
ic view (.dspf file) back
ation; switching constraints;
ing factor, and capacitance
ut (GDS); and, a technology
eters.
tic Analysis Flow
in the netlist and the power
.dspf file is fractured into
. The logical equations
tching constraints, are used
9781424468676/10/$26.00 ©2010 IEEE277
Page 2
to construct the pullup and pulldown paths in the CCRs. Next,
currents are calculated for each transistor and interconnect resistor
in the design using matrix solves, per the more detailed flow
description in Section 3. Designlevel power computation is
discussed in Section 4.
Temperature is then estimated for each design element using a 3D
thermal simulation as discussed in Section 5. Power dissipation
numbers for all the design elements are applied as input to the
thermal simulator, which accounts for the selfheating as well as
thermal aggression from hot neighbors. Finally, the effect of
thermal calculation on interconnect EM is presented in Section 6
along with results in Section 7.
3. STATIC CURRENT CALCULATION
Given the set of legal paths as computed in Section 3, this section
explains the calculation of worstcase IDC, IRMS in every
interconnect segment and transistor in the CCR. For every legal
path, the corresponding netlist and RC network is devolved into a
set of linear IR systems, as shown in Figure 2.
Figure 2: RC Network Converted to a Linear IR System
For each pullup path, devices that are off are removed from the
network, and devices that are on are replaced by equivalent on
resistances inversely proportional to device width (RP1, RP2). Each
parasitic interconnect capacitor (C1, C2) is replaced with a current
source calculated as I = C·ΔV·f. Each diffusion (CDP1, CDP2) and
gate (CGPL, CGNL) device parasitic capacitance on the CCR is
linearized and similarly replaced with a current source. The
voltage swing, ΔV, which defaults to VDD, can be explicitly set on
a pernet basis to model more accurately those nets that do not
swing fullrail. All pulldown paths are similarly enumerated, and
the polarity of the current sources is reversed.
It is important to note the activity factor is set to one for this step,
so the same set of matrix solves can be used to calculate both DC
and RMS currents. This reuse technique is similarly used in the
chargebased approach described in [5]. For each pullup/down
path, the linear IR system is solved to find the current in each
resistor. Absolute current polarity is not important, but relative
polarity is so all the solution results can be analyzed to calculate
these four current values for each interconnect resistor: IFWDMAX:
Maximum positive (forward) current, IFWDMIN: Minimum positive
(forward) current, IREVMAX: Maximum negative (reverse) current,
IREVMIN: Minimum negative (reverse) current
For the simple example in Figure 2, IFWDMAX =IFWDMIN, and
IREVMAX =IREVMIN, but for more complex CCRs, these values will
diverge. The resistor IDC required for EM reliability analysis is:
),(

MINFWDMAXREVMINREVMAXFWDDC
IIII MaxI
⋅−⋅−⋅=
ρρα
(1)
where ρ is the recovery coefficient (~0.9 for copper [13]), and α is
the activity factor of the CCR.
With the simplifying assumption that the current waveform is
triangular in shape, where the peak positive (negative) current is
IPEAKF (IPEAKR), the width of the triangular waveform is equal to
the CCR output rise/fall time (tR), and T is the period of
integration, IRMS can now be derived:
)(
3
)(
1
2
PEAKR
2
PEAKF
0
2
r
T
?
RMS
II
T
t
dttI
T
I
+⋅
⋅
==
(2)
IPEAKF (IPEAKR) can now be related back to the normalized current
IFWDMAX (IREVMAX) since IPEAKF = 2·IFWDMAX/fCLK·tR, and T can
be replaced with α and the clock frequency (fCLK) since T =
1/α·fCLK. As a result, IRMS can reuse the original matrix results
used for the DC current calculations:
)(
3
4
f
2
REV

2
FWD

MAXMAX
RCLK
RMS
II
t
I
+⋅
⋅⋅
⋅
=
α
(3)
At the completion of this step each interconnect segment (resistor)
has its DC and RMS currents fully and accurately characterized.
4. POWER ESTIMATION
The power dissipated by the design can be computed in a bottom
up manner starting with all the resistors and devices in the design.
The CCRlevel power can then be computed by selecting pullup
and pulldown paths most likely to cause high temperatures. The
designlevel power can be computed by summing the CCRlevel
power numbers after accounting for switching constraints. The
power dissipated in an interconnect resistor is computed using its
=
IRMS and resistance as
RIP
RMSres
∗
2
The transistor power is computed as follows. During the pullup
operation, the total power drawn by the CCR is ?.C.V2.f, of which
Pcap_up = (?.C.V2.f)/2 is stored in the capacitors, and Pres_up is
dissipated in the resistors. The power dissipated by the transistors
in the pullup path is then computed as
upresupcapuptransistor
PPPfV
.
C
.
__
2
_
.
−−= α
(4)
Here, Pres_up is computed as given in (3) using only the pullup
RMS current (IPEAKR = 0). Similarly, Pres_down can be computed as
given in (3) using only the pulldown RMS current (IPEAKF = 0).
During the pulldown operation, the power stored in the capacitors
is dissipated through the resistors (Pres_down) and through the
transistors in the pulldown path. The pulldown transistor power
is then given as
downresdowncapdowntransistor
PPP
___
−=
(5)
P1
N1
P1
N1
PL
NL
C2
C1
Original
CCR
IDP1
RP2
RP1
IDP2
IDN1
IDN2
IGPL
IC1
IGNL
IC2
IDP1
IDP2
RP2
RP1
IDN1
IDN2
IC1
IC2
IGPL
IGNL
Enumerate Pullup PathEnumerate Pulldown Path
278
Page 3
The power consumed by individual transisto
be obtained by distributing the total power giv
proportional to the area of the transistors. F
transistor power is then computed as sum of
down transistor power numbers. The power d
legal path in the design is then given as
==
path
P
Pe is the power dissipated by an element e in the
of every pullup/down path in the design can t
The final design power is computed after
constraints such as 1hot where only a subset of
at any given time.
5. TEMPERATURE ESTIMATIO
The power computed as described in Section
perform a thermal analysis on the design. By ke
power applied on the resistors and transistors i
possible to accurately capture the temperature
the resolution of interconnect metals, vias and de
section presents the integration of a 3D the
accounts for selfheating as well as thermal dif
dielectric.
The following subsections describe the heat dif
the general heat flow, the methodology and inte
engine and the result validation with silicon data
5.1 3D Thermal Analysis
The thermal analysis methodology is shown
underlying 3D thermal engine used in this w
[14]. Initially, the package boundary condition i
complete package model and a package proces
Flomerics [15]. A reduced package model is ob
of resistances on each side of the die, to model
heat flow out of the die.
Figure 3: 3D Thermal Analysis Meth
Other inputs to the 3D thermal engine include t
format, DSPF data, technology data. Technolo
parameters such as thickness, mask layer inform
properties including thermal conductivities. The
data are used to identify the power dissipating
interconnect resistors and transistors in the desi
design is analyzed either using reflective bound
assumes the design to be replicated in a tiled
possible to analyze the design by placing the d
location in the floorplan to account for real
interaction.
The designlevel power estimated as explained
then imposed on the design layout such that e
resistor and transistor in the design is conver
ors in the path can
ven in (4) and (5)
Finally, the total
pullup and pull
dissipated by any
?
=
1
e
e path. The power
thus be computed.
r accounting for
f elements are ON

e P

path
where
ON
5 can be used to
eeping track of the
n the design, it is
gradient down to
evice fingers. This
ermal engine that
ffusion across the
ffusion models for
egration of the 3D
a.
in Figure 3. The
ork is FireBolt™
is resolved using a
ssing tool such as
btained, consisting
the conduction of
hodology
the layout in GDS
ogy data includes
mation and material
e GDS and DSPF
g regions such as
gn. The candidate
dary condition that
fashion. It is also
design in its exact
neighbor thermal
d in Section 5.3 is
every interconnect
rted into a power
source. The 3D thermal engine then c
temperature map of the design. The 3
provides temperature for every interco
in the design and can be used to
reliability analysis of the design. We
flow and the tool with silicon EM tes
the maximum error is only about 1°C.
6. RELIABILITY ANALY
This section discusses the calculation o
currents and temperature of desig
lognormal failure distribution [1, 6], th
single interconnect interface is:
??
?
?
??
?
?
⋅
Φ=
σ
)))(/(ln(
50
iLIFE
n
DC
FAILi
TTTS
P
where Φ is the standard normal cumu
SDC is the ratio IDC/IDCLIMIT, n is a weig
target product lifetime, T50(Ti) is the
the metal temperature, and σ is s
distribution. T50 is typically characteriz
TJ. The parameters n, T50(TJ), and σ
process data.
The relationship between temperature
known via Black’s equation [11]:
??
?
?
??
?
?
⋅
⋅⋅=
−
DC
iB
A
n
i
Tk
E
jATT
exp)(
50
where A is a processdependent cons
density, EA is the activation energy
constant. Assuming a single EM failur
the combined probability of a chip failu
∏
=
i
−−=
N
FAILi
P
CHIP

FAIL
P
1
)1 (1
A commonly used reliability term is F
109 product hours. A value of 1 FIT ro
in 1,000 failing after 10 years, and is r
as:
CHIPFAIL
LIFE
CHIP
P
T
hr
FIT

9
.10
⋅=
The total FIT for the design is comput
both interconnects and transistors. To
central database recorded the FIT
maintained a running total of chip FIT
a prebudgeted FIT value to target (FI
database enabled FITswapping so blo
full budgeted FIT value could give so
speedup EM closure.
7. OPERATION AND RES
This section discusses the results ob
methodology. First, the thermal map
presented to underscore the importanc
in reliability analysis. Next, results
methods are compared against the disc
computes a high resolution
3D thermal estimation step
nnect resistor and transistor
perform a high resolution
e validated the 3D thermal
st structures and found that
YSIS
of chip failure rate from DC
n elements. Assuming a
he probability of failure of a
(8)
ulative distribution function,
ghting exponent, TLIFE is the
halflife for wire failure at
standard deviation of the
zed at junction temperature,
are derived from measured
(in Kelvin) and T50 is well
(9)
stant, jDC is the DC current
y, and kB is Boltzmann’s
re will cause a chip failure,
ure can be expressed as [6]:
(10)
FIT, which is one failure per
oughly corresponds to 1 part
related to failure probability
(11)
ed as the sum of FIT due to
o accelerate design time, a
value for all blocks, and
T rate. Each block was given
T/N blocks), but the central
ocks that did not need their
me or all to other blocks to
SULTS
btained using the discussed
p of an example design is
ce of 3D thermal simulation
obtained using alternative
ussed methodology.
279
Page 4
7.1 Thermal Analysis of an Example Des
An example fullcustom block designed in 45
analyzed. The design has close to 800,000 transi
CCRs, and operates on flat, transistorlevel ex
total number of powergenerating elements, inc
interconnect, is about 4.5 million. Utilizing 30 p
maximum run time was 8 hours, which inclu
thermal simulation. Figure 4 shows the ther
example block (E). It was simulated in context
and cache both kept at an uniform power densi
be given different power patterns. Power for the
across the entire GDS, including various metal
is applied on the active region for the rest of th
The hot spots seen in Figure 4 can be traced ba
metal, or a device.
Figure 4: Thermal Map of the E B
7.2 Interconnect Reliability
This subsection showcases the benefits of ac
switching constraints, power and temperature of
Table 1 contains results obtained from the reliab
set of custom logic designs. The Design Data c
total number of parasitic resistors (Rs) in each
numbers column shows the failure rate of the des
described in Section 6.
Design Data FIT Re
Name Rs 3D
Thermal
Cons T
(AVG)
Des1 232K 2.6e03 4.1e04
Des2 1.05M 3.6e05 2.9e06
Des3 2.37M 1.3e05 4.9e07
Table 1: FIT Rate Computatio
The column under 3D Thermal presents result
the 3D thermal estimation step discussed in
column under Const T presents failure rate nu
using the average (Avg) temperatures as obtai
thermal analysis. As expected, if a design co
number of hot (or cold) design elements, a
temperature on the design elements can lead
pessimistic) failure rate numbers.
The column under selfheating shows the fail
obtained using the temperature estimates that dep
individual power densities of design elements. T
a design element is a function of its length. F
density, the temperature rises with length until
length is reached after which the temperature a
length reaches a steady state. If a design contains
sign
nm technology is
istors and 150,000
xtracted data. The
luding device and
parallel CPUs, the
uded the full 3D
rmal map of the
to the entire core
ity. They can also
e E block is spread
layers, whereas it
he core and cache.
ck to a single via,
Block
ccurately handling
f analyzed designs.
bility analysis of a
column shows the
h design. The FIT
signs computed as
esults
T
)
Selfheat
4 3.0e04
6 2.5e05
7 1.6e+01
on
s computed using
n Section 5. The
umbers computed
ined from the 3D
ontains significant
assuming average
to optimistic (or
lure rate numbers
pend solely on the
The temperature of
For a given power
the characteristic
along the element
s elements that are
shorter than the characteristic length, t
by selfheating models can be pess
heating models do not capture neigh
aided by cold neighbors.
8. CONCLUSIONS
This paper presented a thermalaware
the effects of design topology, currents
A 3D thermal analysis step was d
temperature of the designs at res
resolution and was used to verify re
designs. The results obtained using t
was compared against alternative appr
the importance of 3D thermal analysis.
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280