Analysis of DC-Link Capacitor Losses in
Three-Level Neutral Point Clamped and Cascaded
H-Bridge Voltage Source Inverters
Georgios I. Orfanoudakis*, Suleiman M. Sharkh* and Michael A. Yuratich†
* University of Southampton, UK
† TSL Technology, UK
Abstract-Loss estimation is a critical aspect of inverter design.
The present work investigates the losses occurring in the
DC-link capacitors of the three-phase three-level Neutral Point
Clamped and Cascaded H-Bridge inverter topologies, by
performing a harmonic analysis of the capacitor currents.
Results are verified by simulations. Their analysis reveals the
advantage of the NPC inverter.
An essential part of voltage source inverter (VSI) design is
the selection of DC-link capacitors. The capacitors are a
sensitive element of the inverter and a common source of
inverter failures. Capacitor lifetime is highly affected by
thermal stresses that occur due to internal capacitor losses.
DC-link capacitor losses can be significant, hence shortening
the capacitor lifetime and decreasing the inverter power
output. An accurate estimate of these losses can contribute in
the design processes of sizing the inverter DC-link capacitors
and estimating the efficiency of the inverter.
Losses in a DC-link capacitor occur because of its
Equivalent Series Resistance (ESR). The rms value of the
total current flowing through a capacitor can provide a first
approximation for its losses. The literature contains rms
expressions for the capacitor current of the two-level  – 
and the three-level Cascaded H-Bridge inverters . Use of
these expressions for loss estimation assumes a fixed ESR
value. However, the ESR is a function of the frequency of the
capacitor current , . Since the current of a DC-link
capacitor comprises several harmonics located at different
frequencies, it is necessary, for accurate calculation of losses,
to determine the rms values of the capacitor current
harmonics and use the appropriate value of ESR for each
harmonic. The losses can be then estimated as the sum of the
losses caused by the different harmonics.
A harmonic analysis of DC-link capacitor current has been
derived in  for the two-level inverter. This paper extends
this analysis to the three-level Neutral Point Clamped (NPC)
and Cascaded H-Bridge inverters topologies. The resulting
current spectra and a capacitor ESR – frequency characteristic
are used to provide estimates of the DC-link capacitor losses
in the two three-level topologies as well as the two-level
Losses are also estimated using the rms value of the total
capacitor current and a single value for the ESR. The three
topologies are compared on the basis of both of these
estimates. Throughout the analysis, a ripple-free DC current
is assumed to be supplied by the inverter DC sources.
Section II gives a description of capacitor ESR
characteristics and relates them to expressions used for
estimating capacitor lifetime. Section III presents expressions
for the rms values of the DC-link current in the three
topologies and uses these values to calculate the DC-link
capacitor losses based on a constant value of the ESR. The
method that is used for the analysis of DC-link current
harmonics is summarized in Section IV, along with the results
of its application to a two-level inverter. Section V contains
the main part of the present work, which is concerned with
the derivation of the analytical expressions for the DC-link
current spectra of the three-level Neutral Point Clamped
(NPC) and Cascaded H-Bridge inverters. The results are
presented and validated in Section VI. The comparison
between the three topologies is included in the same section.
Section VII discusses the use of capacitor total current rms
expressions and a fixed value of ESR for loss estimations and
Section VII summarizes the final conclusions.
CAPACITOR ESR CHARACTERISTICS
The Equivalent Series Resistance of a DC-link capacitor
varies with the frequency of the capacitor current. A typical
ESR – frequency characteristic is illustrated in Fig. 1 .
In case that more than one current harmonics h, with rms
values Ih,rms and frequencies fh flow through the capacitor, the
losses P occurring on the capacitor’s ESR can be calculated
using equation (1) below, where RC(fh) stands for the value of
ESR at frequency fh.
Losses affect the capacitor lifetime, since they cause heat
dissipation and thermal stress. A factor KRipple is used by
capacitor manufacturers to quantify the effect of current
ripple on capacitor lifetime.
00.2 0.40.60.8 1
Capacitor Losses (W)
2-L / NPC
Fig. 1. ESR – frequency characteristic of a 4.7mF / 450V capacitor .
KRipple is given by the following equation :
where ∆T0 represents the increase in capacitor core
temperature due to the rated ripple current, I0 and f0 represent
the rated ripple current’s amplitude and frequency, and Ih and
fh represent the amplitude and frequency of current harmonic
h. Fh is a current multiplier given in data sheets or derived
from the ESR characteristic.
DC-LINK CURRENT RMS VALUES
The rms value of the capacitor current can provide a first
approach to estimating its losses, using the equation below:
The use of rms values for the estimation of losses implies
an assumption of constant capacitor ESR value RC,
throughout the whole frequency range. Section VII examines
the conditions under which this assumption can lead to
acceptable loss estimations. Equations that give the current
rms values of the two-level and three-level NPC and
Cascaded H-Bridge inverters are included in the Appendix.
Their derivation for the case of the two-level inverter can be
found in  – . The three-level inverter equations are part
of unpublished work . An equivalent result for the
Cascaded H-Bridge inverter is also found in . It is
important to note that the two-level inverter has the same rms
value of capacitor current as the three-level NPC inverter. An
rms-based loss estimation gives equal results for these two
topologies and higher values for the Cascaded H-Bridge
inverter. Fig. 2 illustrates the variation of capacitor losses
with Modulation index for the three topologies. The values of
the expression parameters are summarized in Table I.
Fig. 2. Capacitor losses estimated using total current rms expressions.
LIST OF PARAMETERS
Symbol Quantity Value Unit
Load power factor
DC-LINK CURRENT HARMONICS
A more accurate approximation of DC-link capacitor losses
requires a harmonic analysis of the capacitor current. The
method used to analytically derive the current spectra is the
well-known geometric wall model, introduced by H. S. Black
in . The method has been widely applied for analyzing the
harmonics of the output voltage of different inverter
topologies and PWM strategies . The authors of  used
this model for the analysis of the DC-link capacitor currents
of a two-level inverter. The resulting spectra are combined
with the ESR characteristics as shown in (1) to provide a
more accurate estimation of the losses than that provided by
A. Summary of Black’s Geometric Wall Model
The geometric wall model provides an alternative way for
representing the process of pulse generation in PWM
converters. The carrier and reference waveforms are redrawn
in a transformed plane, so that the intersections between the
new waveforms define the same train of pulses as the original
PWM method. The carrier waveform in this plane turns into a
straight line (assuming natural sampling) and the reference
waveform is transformed accordingly to form closed regions
referred to as contour plots. The width of the generated pulses
is periodic with respect to both dimensions of the new plane.
The function that describes the pulse train can therefore be
written as a double Fourier series. The Fourier analysis results
in a spectrum that plots the function in the frequency domain.
B. Analysis of DC-Link Capacitor Current using the
Geometric Wall Model
The geometrical wall model has been widely applied for
the harmonic analysis of voltage pulse trains, as mentioned
earlier. The model provides the points of waveform
intersections that define the pulse widths. These points are
used to chop a constant waveform, whose amplitude is equal
to the pulse height, and convert it to a pulse train. When
studying converter output voltages, this constant waveform is
the DC-bus voltage.
In the case of DC-link capacitor current, the waveform that
has to be chopped is a sinusoidal output current of the
inverter (assuming in this paper a sinusoidal current at
fundamental frequency). For the cases of integer carrier to
fundamental frequency ratios only, the resulting (chopped)
current waveform is periodic, so it can be analyzed by the
geometrical wall model and expressed as a double Fourier
series. However, an extension of the Fourier coefficient
integrals (see (4) for example) over a large number of
fundamental periods also yields identical expressions for the
Fourier coefficients, while covering the cases of non integer
frequency ratios .
The DC-link capacitor current harmonics of a two-level
inverter were analyzed in . The derivation was based on
the current of the IGBT/Diode module V1 of phase A that is
connected to the positive-end of the inverter’s DC-bus. The
Fourier coefficients of this current were proved to be given by
(4) below, where M(y) is the function that defines the voltage
reference waveform and IL represents the amplitude of the
The respective coefficients for the currents of the upper
modules V3 and V5 of inverter phases B and C are given by
(4), multiplied by e+2jnπ/3 and e-2jnπ/3, respectively. Since the
capacitor current is the complex sum of these three module
currents, excluding the DC component that is assumed to
come from the DC source, the capacitor current Fourier
coefficients can be calculated using the following equation:
DC-LINK CURRENT HARMONICS OF THREE-LEVEL
A. Neutral Point Clamped Inverter
As in the two-level inverter, the instantaneous current
flowing through the DC-link capacitor of the NPC inverter is
the complex sum of the currents through the inverter’s three
upper modules (V1A, V1B, V1C), shown in Fig. 3. Harmonic
analysis of one of these module currents is sufficient to
calculate the DC-link capacitor current harmonics.
The following solution is given for the three-level Phase-
Disposition Pulse Width Modulation (PD PWM) method
using two in-phase triangular carriers and a sinusoidal
reference waveform. The application of the geometric wall
model to the three-level PD PWM results into the wall model
contour plot illustrated in Fig. 4 . According to this plot,
the output voltage for phase A is positive only in the closed
region at the center of the graph. Hence, this is the region
where module V1A carries the current of phase A. The
complex Fourier coefficients of iV1A will therefore come from
The results are summarized in the Appendix. The capacitor
current coefficients are given by a complex sum like (5), for
modules V1A, V1B and V1C.
Fig. 3. Three-phase three-level Neutral Point Clamped inverter.
Fig. 4. Contour plot for the three-level PD PWM method .
Estimated Mag. (A)
Simulated Mag. (A)
Estimated Mag. (A)
Fig. 7. Estimated and simulated spectra of the Cascaded H-Bridge inverter.
Simulated Mag. (A)
B. Cascaded H-Bridge Inverter
Unlike the NPC inverter, the current of each capacitor in
this topology is only determined by the operation of the
respective H-Bridge. Hence, the derivation of a capacitor
current is not given by an equation in the form of (5). The
current that will be harmonically analyzed for this topology
will be idA, as shown in Fig. 5. The AC component of this
current flows through the DC-link capacitor of phase A.
Since the purpose of the present analysis is to perform a
comparison between inverter topologies, it is important to
select a switching method for the Cascaded H-Bridge inverter
that is equivalent to PD PWM for the NPC inverter. A
discontinuous PWM method, that yields equal switching
losses and the same output voltage spectra for the two
topologies, is described in pages 504 – 506 of . Pulse
generation is again based on the contour plot of Fig. 4. The
output voltage for phase A is positive in the region at the
center of the plot and negative in the regions at the edges. The
current idA of the Cascaded H-Bridge inverter is therefore
equal to the phase current iA, or the opposite of it (-iA) in the
respective regions. Its Fourier coefficients are given by (7).
The Appendix contains the detailed results. Apart from the
DC component, the capacitor current of phase A is
harmonically described by the coefficients of idA.
Fig. 5. Three-phase three-level Cascaded H-Bridge inverter.
VALIDATION OF DC-LINK CURRENT SPECTRA AND
COMPARISON OF INVERTER LOSSES
The two three-level inverter topologies were simulated in
the SimPowerSystems Toolbox of Matlab – Simulink. This
Section presents the DC-link current spectra derived using the
results of the harmonic analysis and compares them with the
spectra that were taken from the simulations. Fig. 6 and Fig. 7
illustrate representative results for the NPC and Cascaded
H-Bridge inverters, respectively, for the operating parameters
summarized in Table I and a Modulation index equal to 0.85.
The analytically-derived spectra
simulations for a wide range of operating parameter values
(Modulation index, load power factor, fundamental and
Based on the results of the harmonic analysis, DC-link
losses were estimated assuming that the capacitor ESRs
follow the characteristic of Fig. 1. The NPC and the Cascaded
H-Bridge inverters use two and three of these capacitors, as
shown in Fig. 3 and Fig.5, respectively. The two-level
inverter that is also included in the comparison uses two
capacitors, connected in series.
were validated by
Fig. 6. Estimated and simulated spectra of the NPC inverter.
00.2 0.40.6 0.81
Capacitor Losses (W)
Fig. 8. Capacitor losses estimated using harmonic analysis
A plot of the estimated DC-link losses of the three
topologies against the Modulation index is shown in Fig. 8.
The plot indicates that the Cascaded H-Bridge inverter has
the highest amount of losses. The losses in the DC-link of the
NPC inverter are significantly lower, while from the same
aspect, the two-level inverter is the most efficient among the
Comparison of the two plots in Fig. 2 and Fig. 8 reveals
that for the three-level topologies there is a notable deviation
between the loss estimations based on the DC-link current
rms expressions which assume a constant capacitor ESR, and
the harmonic analysis, respectively. In contrast, the
estimations are similar for the case of the two-level inverter.
This difference is attributable to the shape of the electrolytic
capacitor ESR characteristics.
A close examination of ESR characteristics of electrolytic
capacitors indicates that their ESR decreases for harmonic
frequencies between 50 Hz and 1 kHz, while it remains
approximately constant for higher frequencies. Additionally,
inverter switching (carrier) frequencies are commonly higher
than 1 kHz. As a result, the majority of carrier and sideband
harmonic groups, which appear around multiples of the
switching frequency, belong in the constant-ESR frequency
range. Fundamental and baseband harmonics, however, have
to be associated with higher ESR values, according to (1).
Loss estimation based on current rms expressions (3) fails to
treat these harmonics separately, which results in an
underestimation of DC-link capacitor losses for the three-
level inverters. The DC-link capacitor current of the two-level
inverter on the other hand does not contain any fundamental
or baseband harmonics . Hence, the respective rms
expression and the harmonic analysis give similar results for
It is worth mentioning that in the common case of an
inverter that uses electrolytic capacitors for its DC-link and
switches at a moderate frequency, a complete harmonic
analysis may not be necessary for the estimation of losses.
The capacitor current rms expressions can be used according
to (8) below to provide DC-link capacitor loss estimations.
Harmonic analysis is still necessary to obtain the amplitudes
and frequencies of fundamental and baseband harmonics, but
does not need to extend to carrier and sideband harmonics.
The subscripts F/B under the sums in (8) denote that they
refer to the fundamental and baseband harmonics only. In the
second term, RC corresponds to the high frequency constant
value of the ESR.
Equation (8) is not applicable to inverters that operate at
low switching frequencies or use capacitors with different
ESR characteristics. In these cases, certain carrier – sideband
harmonic groups may belong to the low frequency ESR
region and therefore the results of a complete harmonic
analysis should be used according to (1).
Two-level inverters generally switch at lower frequencies
compared to three-level inverters with the same power output,
because of their higher voltage-rated power semiconductor
modules. They are therefore more likely to have low
frequency carrier and sideband harmonics. Increased ESR
values for these harmonics can decrease or reverse the
advantage that the two-level inverters have over the three-
level topologies, and particularly the NPC.
This paper investigated the losses occurring in the DC-link
capacitors of the three-level NPC and Cascaded H-Bridge
inverter topologies. The three-level NPC inverter was proved
to have a significant advantage over the Cascaded H-Bridge
inverter in terms of its DC-link losses. The two-level inverter
that was also examined performs better than both the three-
level topologies, under the assumption of similar switching
frequencies. In practice, a two-level inverter may need to
switch at a lower frequency than the NPC due to using higher
voltage devices, in which case its capacitor losses may be
higher than those of the NPC inverter.
Loss estimations obtained by harmonic analysis were
compared with estimates based on total DC-link capacitor
current rms expressions. The comparison indicated that the
latter are likely to underestimate the capacitor losses of three-
level inverters because they use a fixed value for the capacitor
ESR. However, fundamental and baseband harmonics can be
combined with the total rms current expressions to give more
accurate estimates of capacitor losses.