Conference Paper

Analysis of DC-Link capacitor losses in three-level neutral point clamped and cascaded H-Bridge voltage source inverters

Univ. of Southampton, Southampton, UK
DOI: 10.1109/ISIE.2010.5637820 Conference: Industrial Electronics (ISIE), 2010 IEEE International Symposium on
Source: IEEE Xplore

ABSTRACT Loss estimation is a critical aspect of inverter design. The present work investigates the losses occurring in the DC-link capacitors of the three-phase three-level Neutral Point Clamped and Cascaded H-Bridge inverter topologies, by performing a harmonic analysis of the capacitor currents. Results are verified by simulations. Their analysis reveals the advantage of the NPC inverter.

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    ABSTRACT: The DC capacitor is an important component in a voltage source inverter. The RMS current flowing through the capacitor determines the capacitor size and losses. The losses, in turn, influence the capacitor life. This paper proposes a space vector based modulation strategy for reducing the capacitor RMS current in a three-level diode-clamped inverter. An analytical closed-form expression is derived for the DC capacitor RMS current with the proposed PWM strategy. The analytical expression is validated through simulations and also experimentally. Theoretical and experimental results are presented, comparing the proposed strategy with conventional space vector PWM (CSVPWM). It is shown that the proposed strategy reduces the capacitor RMS current significantly at high modulation indices and high power factors.
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