0.84 ps Resolution Clock Skew Measurement via Subsampling

Dept. of Electr. Commun. Eng., Indian Inst. of Sci., Bangalore, India
IEEE Transactions on Very Large Scale Integration (VLSI) Systems (Impact Factor: 1.36). 01/2012; 19(12):2267 - 2275. DOI: 10.1109/TVLSI.2010.2083706
Source: IEEE Xplore


An all-digital on-chip clock skew measurement system via subsampling is presented. The clock nodes are subsampled with a near-frequency asynchronous sampling clock to result in beat signals which are themselves skewed in the same proportion but on a larger time scale. The beat signals are then suitably masked to extract only the skews of the rising edges of the clock signals. We propose a histogram of the arithmetic difference of the beat signals which decouples the relationship of clock jitter to the minimum measurable skew, and allows skews arbitrarily close to zero to be measured with a precision limited largely by measurement time, unlike the conventional XOR based histogram approach. We also analytically show that the proposed approach leads to an unbiased estimate of skew. The measured results from a 65 nm delay measurement front-end indicate that for an input skew range of ±1 fan-out-of-4 (FO4) delay, ±3σ resolution of 0.84 ps can be obtained with an integral error of 0.65 ps. We also experimentally demonstrate that a frequency modulation on a sampling clock maintains precision, indicating the robustness of the technique to jitter. We also show how FM modulation helps in restoring precision in case of rationally related clocks.

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Available from: Rajath Vasudevamurthy, Oct 02, 2015
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