Conference Proceeding

Investigation of current flow during wafer-level CDM using real-time probing

11/2010; pp.1 - 10 In proceeding of: Electrical Overstress/ Electrostatic Discharge Symposium (EOS/ESD), 2010 32nd
Source: IEEE Xplore

ABSTRACT Using real-time voltage probing and circuit simulation, the stress induced by wafer-level CDM test methods is compared to that of package-level FICDM testers. It is shown that while wafer-level testers can replicate I/O failures, they may not replicate core failures because of differences in the induced current stress.

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Keywords

circuit simulation
 
package-level FICDM testers
 
wafer-level CDM test methods
 
wafer-level testers
 

N. Jack