Investigation of current flow during wafer-level CDM using real-time probing
ABSTRACT Using real-time voltage probing and circuit simulation, the stress induced by wafer-level CDM test methods is compared to that of package-level FICDM testers. It is shown that while wafer-level testers can replicate I/O failures, they may not replicate core failures because of differences in the induced current stress.
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ABSTRACT: A newly designed on-chip voltage monitor circuit (VM) is capable of recording for subsequent readout the peak voltage reached at internal nodes during ESD events. Real-time voltage probing techniques during wafer-level CDM are verified using VMs; guidelines are discussed for reducing the impact of probing on current flow.01/2011;