Conference Proceeding
A 50-300-MHz low power and high linear active RF tracking filter for digital TV tuner ICs
Korea Adv. Inst. of Sci. & Technol., Daejeon, South Korea
Proceedings of the Custom Integrated Circuits Conference
10/2010;
DOI:10.1109/CICC.2010.5617462
pp.1 - 4 In proceeding of: Custom Integrated Circuits Conference (CICC), 2010 IEEE
Source: IEEE Xplore
- Citations (5)
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Cited In (0)
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Article: A single-chip tuner for DVB-T
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ABSTRACT: A new architecture is presented for a single-chip tuner for digital terrestrial television, based on existing double conversion and direct conversion topologies. The new design forms part of a mixed-signal Digital Video Broadcasting-Terrestrial (DVB-T) receiver system, employing digital signal processing at baseband to ensure minimal performance requirements for the analog circuitry. To evaluate the potential performance of this new tuner/receiver system, high-level system simulations have been performed, followed by the construction of a prototype DVB-T receiver using a custom-designed analog ASIC which integrates all analog tuner blocks (including channel filtering) on one chip. Measured results from this chip, implemented in a 20-GHz bipolar technology, show an overall third-order input referred intercept point of 116 dBμV, a noise figure of 14 dB and an automatic gain control range of 71.4 dB, drawing 250 mA at a 5-V supply.IEEE Journal of Solid-State Circuits 09/2003; · 3.23 Impact Factor -
Conference Proceeding: On-chip auto-calibrated RF tracking filter for cable silicon tuner
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ABSTRACT: An integrated RF tracking filter based upon a programmable LC resonator and an auto-calibration is presented. Its 10 dB unwanted power rejection improves the tuner performance above 54 dB CNR and 57 dB C/I under loaded spectrum conditions. This filter enables a low-cost high-performance silicon tuner for both analog and digital Set-Top-Boxes and Cable Modems.Solid-State Circuits Conference, 2008. ESSCIRC 2008. 34th European; 10/2008 -
Article: A 200-MHz seventh-order equiripple continuous-time filter by design of nonlinearity suppression in 0.25-μm CMOS process
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ABSTRACT: Seventh-order equiripple filter with cutoff frequency of 200 MHz is developed in CMOS 0.25-μm process. A new design method has been adopted to obtain enough accuracy and linearity in high-frequency operation. Optimal device sizes are determined, which maximize the accuracy. The most suitable filter configuration is determined, which suppresses the influence of the nonlinearity of the transconductors over the linearity of the filter. Experimental results satisfied group delay variation of ±5% and achieved total harmonic distortion of less than 1% for 800 mV<sub>ppd</sub> differential inputIEEE Journal of Solid-State Circuits 06/2002; · 3.23 Impact Factor
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Keywords
38 dB 3rd order harmonic rejection
6 dB unwanted signal rejection@N+6 channel
Digital TV tuner ICs
dynamic source degenerated differential pair
linearity performance
linearized transconductor
local oscillator harmonic
low power
maximum IIP3
negative resistance load
proposed low power
Q RF
transconductor linearization technique