BJT-mode endurance on a 1T-RAM bulk FinFET device

IMEC, Leuven, Belgium
IEEE Electron Device Letters (Impact Factor: 2.75). 01/2011; 31(12):1380 - 1382. DOI: 10.1109/LED.2010.2079313
Source: IEEE Xplore


In this letter, endurance is investigated on one bulk FinFET transistor capacitorless random access memory, using the bipolar junction transistor (BJT) programming mode. For the first time, it is shown that endurance is an issue using the BJT-mode programming. The dominant degradation is due to the interface state generation by impact ionization used to write “1.” This degradation leads to the gate-induced drain leakage current increase, which results in shifts of the read state “0” current.

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    • "In addition, bulk FinFETs are also investigated for use in future one-transistor (1T) capacitorless memory devices [1]. While encouraging results have been obtained so far [2], [3], there are some outstanding issues, such as the hot-carrier degradation [4] induced by the programming, either relying on the gateinduced drain leakage or the bipolar junction transistor mode [4]. Such effects can be reduced by channel or source–drain Manuscript received November 29, 2011; revised January 24, 2012; accepted January 26, 2012. "
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    ABSTRACT: The low frequency (LF) noise has been studied in n-channel triple-gate bulk fin Field-Effect Transistors (FinFETs), which are developed for one-transistor (1T) memory applications. Significant variation in the noise spectral density has been observed, which is related to the random occurrence of excess Lorentzian components, associated with generation– recombination (GR) noise. Both gate-voltage-dependent and gatevoltage- independent GR noise peaks have been found, which are assigned to gate oxide traps or traps in the silicon fins, respectively. In addition, excess 1/f noise in weak inversion has sometimes been observed and is ascribed to surface-roughness fluctuations. Overall, the gate oxide quality seems to be the major contributor to the LF noise and not the channel and source–drain engineering investigated here.
    IEEE Transactions on Electron Devices 05/2012; 59(5):1272. DOI:10.1109/TED.2012.2186815 · 2.47 Impact Factor
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    • "Owing to the current gain from the parasitic bipolar transistor, the sensing margin of the Gen 2 scheme is more than 50 μA/μm in general [20]–[22]. However, a high drain bias of more than 3 V is necessary to achieve this high sensing margin, which causes several reliability issues [5]. Unfortunately, the reliability and the endurance issues in the Gen 2 scheme have not been studied comprehensively thus far. "
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    ABSTRACT: A novel bias scheme is demonstrated for performance improvement of floating-body cell memory, particularly retention time. Its basic mechanism is based on carrier lifetime engineering, which takes advantage of generation lifetime that is longer than recombination lifetime. In addition, the proposed scheme is suitable for low-power operation; a high drain bias is unnecessary to generate excess carriers, which allows reliable endurance of up to $\hbox{10}^{12}$ switching instances at 85 $^{\circ}\hbox{C}$.
    IEEE Transactions on Electron Devices 02/2012; 59(2):367-373. DOI:10.1109/TED.2011.2176944 · 2.47 Impact Factor
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    ABSTRACT: The reliability of a one Transistor Floating Body Random Access Memory (1T-FBRAM) bulk FinFET cell using Bipolar Junction Transistor (BJT) programming is investigated. It is shown that hot holes generated by impact ionization create interface defects close to the drain and positively charged oxide traps, especially at high transverse electric field. These created defects degrade the cell endurance. Moreover, this degradation is enhanced for shorter channel devices and narrower fin widths, which would be a limitation for the scaling of floating body RAM. Keywords-Floating body cell; RAM; endurance; cycling; BJT; FinFET.
    01/2011; DOI:10.1109/IRPS.2011.5784459
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