BJT-Mode Endurance on a 1T-RAM Bulk FinFET Device
ABSTRACT In this letter, endurance is investigated on one bulk FinFET transistor capacitorless random access memory, using the bipolar junction transistor (BJT) programming mode. For the first time, it is shown that endurance is an issue using the BJT-mode programming. The dominant degradation is due to the interface state generation by impact ionization used to write “1.” This degradation leads to the gate-induced drain leakage current increase, which results in shifts of the read state “0” current.
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ABSTRACT: This paper assesses one Transistor Floating Body Random Access Memory (1T-FBRAM) in Bulk FinFET devices as a candidate for conventional DRAM replacement in the future technology nodes. For the cell operation, Bipolar Junction Transistor (BJT) programming is used. Reliability and retention time of the floating body effect are studied on different gate lengths, fin widths and for different programming biases. The degradation mechanisms during cycling are identified. The optimum number of cycles extracted (~109) is still far below the 1016 cycles expected. Long retention times are obtained; however, with the tail bit distribution below the 64ms DRAM specifications. Besides, the generated floating body takes place beneath the drain at the n+/p+ drain/ground-plane junction, which explains the long retention times by the large junctions area. Moreover, the floating body can be obtained only by leaving floating the bulk contact of the bulk FinFET cell, which makes its integration in a DRAM chip challenging. On the other hand, the bulk FinFET device shows a biristor like behaviour but featuring more options by the use of the gate to control the write and read.Microelectronics and Solid State Electronics. 06/2012; 1(2).
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ABSTRACT: The long-term endurance characteristics are investigated for MOSFET-based capacitorless one-transistor DRAM (1T-DRAM) under the conventional versus biristor mode. Based on the experimental results and on a supporting simulation study, it was found that the MOSFET-based 1T-DRAM, when enabled by a biristor mode, is preferred for long-term endurance compared with MOSFET-based 1T-DRAM when operated in a conventional mode. Although a high drain voltage is required in the biristor mode for programming, improved endurance characteristics are observed. The simulation study showed that this feature is achieved by the suppression of hot-hole-induced degradation, which arises from the absence of a gate use at the dynamic cell. Thus, this letter provides a new type of device architecture as well as a novel and innovative operational method pertaining to conventional 1T-DRAM to mitigate the problem of limited endurance.IEEE Electron Device Letters 01/2014; 35(2):220-222. · 2.79 Impact Factor
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ABSTRACT: The low frequency (LF) noise has been studied in n-channel triple-gate bulk fin Field-Effect Transistors (FinFETs), which are developed for one-transistor (1T) memory applications. Significant variation in the noise spectral density has been observed, which is related to the random occurrence of excess Lorentzian components, associated with generation– recombination (GR) noise. Both gate-voltage-dependent and gatevoltage- independent GR noise peaks have been found, which are assigned to gate oxide traps or traps in the silicon fins, respectively. In addition, excess 1/f noise in weak inversion has sometimes been observed and is ascribed to surface-roughness fluctuations. Overall, the gate oxide quality seems to be the major contributor to the LF noise and not the channel and source–drain engineering investigated here.IEEE Transactions on Electron Devices 05/2012; 59(5):1272. · 2.06 Impact Factor