Conference Paper

4k-point FFT algorithms based on optimized twiddle factor multiplication for FPGAs

Dept. of Electr. Eng., Linkoping Univ., Linköping, Sweden
DOI: 10.1109/PRIMEASIA.2010.5604921 Conference: Microelectronics and Electronics (PrimeAsia), 2010 Asia Pacific Conference on Postgraduate Research in
Source: IEEE Xplore

ABSTRACT In this paper, we propose higher point FFT (fast Fourier transform) algorithms for a single delay feedback pipelined FFT architecture considering the 4096-point FFT. These algorithms are different from each other in terms of twiddle factor multiplication. Twiddle factor multiplication complexity comparison is presented when implemented on Field-Programmable Gate Arrays (FPGAs) for all proposed algorithms. We also discuss the design criteria of the twiddle factor multiplication. Finally it is shown that there is a trade-off between twiddle factor memory complexity and switching activity in the introduced algorithms.

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