A 28-μW EEG Readout Front-End Utilizing a Current-Mode
Instrumentation Amplifier and a Source-Follower-Based LPF
Tan-Tan Zhang, Jin-Tao Li, Pui-In Mak, Mang-I Vai, Peng-Un Mak, Feng Wan and R. P. Martins 1
Biomedical Engineering and Analog and Mixed Signal VLSI Laboratories, University of Macau, Macao, China
1 – On leave from Instituto Superior Tecnico (IST) / TU of Lisbon, Portugal
Abstract—A novel low-power EEG readout front-end featuring
a current-mode instrumentation amplifier (CMIA) followed by a
4th-order gain-compensated source-follower-based lowpass filter
(LPF) is proposed. The CMIA is of current-conveyor topology
and is chopper-stabilized to improve the common-mode noise
rejection and suppress the dc-offset and 1/f noise. The typical
gain-loss problem of source-follower-based LPF is alleviated by
adopting a gain-compensation technique. Optimized in 0.35-μm
CMOS, the achieved CMRR is >100 dB from 0.01 to 16 Hz,
and >90 dB up to 40 Hz. With the chopper stabilization, the
noise voltage density is 248 nV√Hz at 0.01 Hz and 197 nV√Hz at
100 Hz. The power consumption is 28 μW at 3 V.
Electroencephalogram (EEG) reflects the electrical activity of
the brain as a diagnosis reference of Epilepsy and other
neuropathies. In clinical applications, the most relevant signals
spread over 0.3 to 40 Hz with amplitude ranging from 2 μV to
several hundreds of μV. The ultra-low-frequency EEG signal
(below 0.1 Hz) is mainly informative for diagnosis of cerebral
death whose threshold amplitude is 2 μV. Most present clinical
technologies require the patients, who are under a long-time
continuous monitoring, to be connected by a bulky instrument,
which keeps them of their normal routines while causing
discomforts. This discomfort may change the pathological
characteristics of the measured EEG signal and induce possible
diagnosis faults . Thus, ultra-low-power (ULP) and
miniaturized EEG acquisition system is on great demand for
ambulatory clinical practice. The aim is to provide both comfort
and accurate diagnosis for patients, while extending the
applications to health care, entertainment and sport .
The most critical and power consuming building block of
portable EEG measuring system is the readout front-end which
has to dissipate ULP. The front-end instrumentation amplifier (IA)
defining the signal quality has to feature a high common-mode
rejection ratio (CMRR) such that the strong interference from the
mains can be rejected, and to feature a high signal-to-noise (SNR)
ratio to extract the weak biopotential signals. This paper proposes
a novel EEG readout front-end. It is structured by a current-mode
IA (CMIA) followed by an ULP LPF. The block schematic is
depicted in Fig. 1. The CMIA is based on a power-supply current-
sensed current conveyor. Its central principle was reported in 
and was recently gained more attention in biomedical applications
. The proposed CMIA features chopper stabilization for dc-
offset and 1/f noise removals while improving CMRR. The LPF
is based on a 4th-order source-follower-based (SFB) structure.
Different from the existing SFB LPF that employs saturation-
biased transistors and is targeted for high-frequency applications
, this work explores subthreshold-biased SFB LPF for ultra-
low-frequency biomedical applications. The typical gain-loss
problem of SFB LPF is alleviated in this work by adopting a new
CURRENT MODE IA (CMIA)
A. CMIA Circuit Topology
Figure 2(a) shows the block schematic of the proposed CMIA.
It consists of two Op Amps A1 and A2, and a resistor R1 to sense
the differential outputs. A1 and A2 are connected as unity-gain
buffers to convey the differential input voltages on resistor R1.
Since the common-mode voltage cross R1 is expected to be equal
to each other, only differential current ix = (Vinp – Vinn) / R1 will
flow through R1. In order to apply the power-supply current-
sensed technique, two current mirrors CM1 (CM1’) and CM2
(CM2’) are inserted to both positive and negative power-supply
rails of A1 (A2), thus, ix can be copied precisely to the output stage,
which consists of A3 (A4) and R2 (R2’). A3 (A4) is connected as a
trans-resistor to create a virtual ground at the outputs of CM1, 2
(CM1, 2’) and convert ix into voltage via R2 (R2’), generating the
desired output voltage Voutp = ix R2 (Voutn = ix R2’). The overall
differential voltage gain is given by Gd = R2 / R1 or R2’ / R1.
In practice, process variation and mismatches will lead to
non-zero common mode gain, yielding a finite CMRR that can be
where, Ad1, Ad2 and Ac1, Ac2 are differential mode and common
mode gains of A1 and A2, respectively. With CMRR1 = Ad1 / Ac1
and CMRR2 = Ad2 / Ac2, (1) can be re-expressed as,
It indicates that CMRRIA not only depends on the CMRR of each
active core, but also the matching of gain and CMRR .
1/f noise, dc offset,
& improves CMRR
Fig. 1. Proposed EEG readout front-end.
B. Chopper Stabilization
The CMRR of the CMIA can be degraded by the non-zero
common-mode gain, which is either systematic (topology related)
or random (matching related). Chopper stabilization in Fig. 3 has
been an effective technique for suppressing the 1/f noise and dc-
offset of differential circuits. Here, it is particularly relevant to
improve the CMRR. The input chopper is transparent to the input
common-mode signal. Thus, the common-mode signal will be
converted to differential by the non-zero common-mode gain of
the CMIA. The output chopper frequency-translates such a non-
ideal differential-mode output signal to the chopping frequency
such that it can be suppressed by the following LPF. This
mechanism rejects the CMIA’s 1/f noise and dc-offset as well.
C. Circuit Implementation
Figure 2(b) shows the schematic of the CMIA’s OpAmps,
which is of a two-stage topology with Miller compensation. The
current mirrors are built on the output stages of A1 and A2. The
input PMOS differential pair is of large W/L aspect ratio to
minimize the 1/f noise. Table I summarizes the typical
performance metrics of the employed OpAmp. A dc gain of 44
dB and a gain-bandwidth-product of 126 kHz fulfill the targeted
specifications. Special attention has been paid to bias the OpAmp
such that the impedance of its output is less sensitive to mismatch
and process variations. Mismatch of this parameter can degrade
the CMRR of the CMIA  and it is sensitive to R1. The current
mirrors also play a significant role in determining the CMRR.
Figure 2 (c)-(d) shows their schematics. CM1 is of the basic
standard PMOS current mirror structure to copy the current
through M10, whereas CM2 is capable of copying small ac
current by a current-division technique; a transistor is split into
two, i.e. Mn,ac and Mn,dc. Mn,ac is sized to have a very small
trans-conductance gm, such that a tiny ac current can be
conducted. The bias current is conducted by Mn,dc. Vb1 is the
bias voltage of M13 and Vb2 is the same dc voltage of Vs to bias
Mn,dc. The copied current is further adjusted through Mc1 and
Mc2 to improve the accuracy.
For a conventional MOS source follower, due to channel-
length modulation and the transistors’ bulk transconductance, the
gain is less than unity, corresponding to a gain loss when it is
employed to realize a LPF. Typically, the dc-gain loss is in the
order of 3.5 dB for a subthreshold-biased NMOS source follower
(NSF) biquad. In this work, a gain-compensation technique is
proposed as depicted in Fig. 4. The 1st NMOS source follower
(NSF) biquad is gain-compensated by adding a cross-connected
differential pair, which provides an additional gain path to
compensate the gain loss. Obviously, this gain path can degrade
the good linearity of source-follower-based LPF. In order to
balance the linearity and gain loss, the cross-connected
differential pair is only applied to the NSF and is source-
degenerated by Rdeg. The 2nd biquad is a generic PMOS source
follower (PSF), ensuring a good linearity.
GAIN-COMPENSATED SOURCE-FOLLOWER-BASED LPF
The characteristic of the gain-compensated NSF biquad is
analyzed by considering its small-signal half equivalent circuit as
shown in Fig. 5, where gmn1, gmn2, gmp are the trans-conductances
Fig. 2. (a) Current-conveyor-based CMIA. (b) Schematic of the OpAmp. (c) The current mirror CM1. (d) The current mirror CM2.
SIMULATED OPAMP PERFORMANCE.
3-dB Cutoff Frequency
CMRR up to 3 kHz
Power consumption at 3 V
Fig. 3. Chopper stabilization for 1/f noise, dc-offset reduction and
of Mn1, Mn2, Mp, and ro_n1, ro_n2, ro_p, ro_In, are the output
resistances of Mn1, Mn3, Mgc, In, respectively. Assuming the
transistor’s output resistance is much bigger than the reciprocal of
its transconductance under the subthreshold bias condition, the
transfer function of the NSF biquad is given by,
due to the source degeneration of Mp.
Eq. (3) clearly shows that gmgc can boost the dc gain of the biquad.
The capability of gain compensation is mandated by the tradeoff
between linearity, noise and power consumption. The angular
pole frequencyω0 is given by,
The cutoff frequency is proportional to the term
realize a low cutoff frequency, a low transconductance is desired
to minimize the required capacitor size which can occupy a huge
amount of silicon area for this ultra-low-frequency design. All
transistors are in sub-threshold-biased region to minimize the
transconductance gm, which is given by,
where n is the subthreshold slope factor and is of a value close to
1.5; UT is the thermal voltage and is around 26 mV at room
temperature; ID is the drain current. C11 , C12, C21 and C22 are all
differentially terminated to maximize the capacitance per unit
area. In this work, the optimized ID is 200 pA, resulting in ULP
dissipation. The sum of all physical capacitances is minimized to
an impressive value of 37 pF.
The readout front-end is designed and fully characterized in
0.35-μm CMOS with Spectre as the simulator. Figure 6 shows
the harmonic distortion under a single tone test with an 8-Hz
frequency and a 5-mVpp amplitude. The linearity is limited by
the 3rd harmonic which is 60 dB down from the fundamental.
The variable-gain characteristic is demonstrated in Fig. 7, where
the gain is set by the ratio of R2 (R2’) and R1. With the proposed
gain-compensation technique, the gain loss of the LPF is reduced
from 3.6 to 0.6 dB. Figure 8 shows the CMRR performance of
the entire readout front-end. The CMRR is better than 100 dB up
to 16 Hz, and better than 90 dB up to the cutoff frequency of 40
Hz. The noise performances of the CMIA at 0 and 20-dB gain
levels are illustrated in Fig. 9(a). Due to the use of chopper
stabilization, the input-referred noise voltage density is
effectively suppressed to 248 (175) nV/√Hz at 0.01 Hz at 0 (20)
dB gain. The chopper also reduces the 1/f noise corner frequency
from 84 to 1 Hz. At 20-dB gain, the noise performance of the
readout front-end with and without chopper is depicted in Fig.
Fig. 4. Proposed 4th-order SFB LPF with gain-compensated NSF.
Fig. 5. Small-signal half-equivalent circuit of gain-compensated NSF.
Harmonic Distortion (dB)
Fig. 6. Harmonic distortion with 5-mVp-p input @ 8Hz. The gain is
set to 10 V/V; corresponding to a 50-mVp-p input at the LPF.
Differential Gain (dB)
— R2/R1=1 — R2/R1=10 — R2/R1=100 — R2/R1=1000
LPF’s Cut-off = 40 Hz
Fig. 7. Frequency response of the CMIA with 40-Hz LPF’s cutoff.
9(b). The in-band output-referred noise voltage density is around Download full-text
8μV/√Hz. The noise performance of the standalone LPF is
shown in Fig. 12. Due to its simple hardware structure, the in-
band output-referred noise voltage density is just 4.5 μV/√Hz. A
performance summary of the entire readout front-end is given in
This paper has described a novel low-power EEG readout
front-end. It is structured by a current-conveyor-based CMIA
followed by a 4th-order SFB LPF with gain compensation.
Chopper stabilization is applied to effectively suppress the 1/f
noise and dc-offset while boosting the CMRR. The SFB LPF is
biased in the subthreshold region. It achieves the desired huge
time constant with small power and capacitor area. The LPF is
constructed by two ULP SFB biquads in cascade. Since
nonlinearity is dominated by the 2nd biquad, gain-compensation
is applied only at the 1st biquad, minimizing the gain loss to a
sub-dB range (0.6 dB) while keeping a high dynamic range. The
CMRR is 100 dB from 0.01 Hz to 16 Hz, and is 90 dB up to 40
Hz. The power consumption is minimized to 28 μW at 3 V.
This work was supported by the Research Committee of
University of Macau and the Macau Science and Technology
Development Fund (FDCT).
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CMRR>100 dB up to 16 Hz
CMRR>90 dB @ 40 Hz
Fig. 8. CMRR of the entire readout front-end.
Output Referred Noise Voltage
At 20 dB Gain
20 dB Gain
Input Referred Noise Voltage
0 dB Gain
Fig.9. (a) CMIA’s input-referred noise voltage density at 0-dB and 20-
dB gain. (b) Readout front-end’s output-referred noise voltage density
with and without chopper at 20-dB gain.
Output Referred Noise
Voltage Density (uV/√Hz)
Fig. 10. LPF’s output-referred noise voltage density.
Variable Gain (Via R2 and R2’)
Input-Referred Noise Voltage
Density (CMIA with Chopper)
0.35 μm CMOS
1, 10, 100, 1000 V/V
248 nV/√Hz @ 0.01 Hz
197 nV/√Hz @ 100 Hz
> 100 dB (0.01 to 16 Hz)
> 90 dB (up to 40 Hz)
70 dB / Decade
Lowpass Cutoff Frequency
LPF HD3 down from fundamental
(with 50m VP-P input @ 8 Hz)
THD (with 8 Hz 5m VP-P input, 10
27.6 μW (CMIA)
4.3 nW (LPF)