Statistical power analysis for nanoscale CMOS
ABSTRACT With the scaling down of CMOS technology, process variations are becoming significant. Power consumption is a major constraint on IC yield. However, there has been little research on statistical power analysis compared with that on timing analysis. Here, both the static and dynamic power are considered. We characterize a cell library containing mean power. A standard deviation power library is extracted from Monte Carlo simulations. Then, the mean and variance of the power are derived. The proposed technique is validated on benchmark circuits at 35 nm. We compare the results with SPICE simulations and show that the difference is acceptable.
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ABSTRACT: Leakage current is a stringent constraint in today's ASIC designs. Effective parametric yield prediction must consider leakage current's dependence on chip frequency. The authors propose an analytical expression that includes both subthreshold and gate leakage currents. This model underlies an integrated approach to accurately estimating yield loss for a design with both frequency and power limits.IEEE Design and Test of Computers 08/2005; · 1.62 Impact Factor
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ABSTRACT: Recent changes in CMOS device structures and materials motivated by impending atomistic and quantum-mechanical limitations have profoundly influenced the nature of delay and power variability. Variations in process, temperature, power supply, wear-out, and use history continue to strongly influence delay. The manner in which tolerance is specified and accommodated in high-performance design changes dramatically as CMOS technologies scale beyond a 90-nm minimum lithographic linewidth. In this paper, predominant contributors to variability in new CMOS devices are surveyed, and preferred approaches to mitigate their sources of variability are proposed. Process-, device-, and circuit-level responses to systematic and random components of tolerance are considered. Exploratory, novel structures emerging as evolutionary CMOS replacements are likely to change the nature of variability in the coming generations.Ibm Journal of Research and Development 08/2006; · 0.69 Impact Factor
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ABSTRACT: In this paper we have developed analytical models to estimate the mean and the standard deviation in the gate, the subthreshold, the reverse biased source/drain junction band-to-band tunneling (BTBT) and the total leakage in scaled CMOS devices considering variation in process parameters like device geometry, doping profile, flat-band voltage and supply voltage. We have verified the model using Monte Carlo simulation using an NMOS device of 50 nm effective length and analyzed the results to enumerate the effect of different process parameters on the individual components and the total leakage.Low Power Electronics and Design, 2003. ISLPED '03. Proceedings of the 2003 International Symposium on; 09/2003
Statistical Power Analysis for Nanoscale CMOS
Yangang Wang, Michael Merrett and Mark Zwolinski
School of Electronics and Computer Science
University of Southampton, Southampton SO17 1BJ, UK
Abstract—With the scaling down of CMOS technology, process
variations are becoming significant. Power consumption is a
major constraint on IC yield. However, there has been little
research on statistical power analysis compared with that on
timing analysis. Here, both the static and dynamic power are
considered. We characterize a cell library containing mean power.
A standard deviation power library is extracted from Monte
Carlo simulations. Then, the mean and variance of the power
are derived. The proposed technique is validated on benchmark
circuits at 35 nm. We compare the results with SPICE simulations
and show that the difference is acceptable.
In the manufacture of nanoscale CMOS integrated circuits
(IC), more and more process variations arise due to the limi-
tations of physics and technology , . Process variations
can be systematic or random, the former are deterministic and
predictable but the latter are uncertain and include extrinsic
and intrinsic variations. The intrinsic variation is due to atomic
level fluctuations and occurs within a die, which is regarded
as the main source of process variations at nano scales.
The effects include random discrete doping (RDD), line-edge
roughness (LER), oxide thickness (tox) roughness (OTR) and
poly-silicon granularity (PSG) –.
Process variations lead to variations in device characteristics
and IC performance. Timing performance used to be taken as
the IC yield criterion. However, with shrinking gate length (L),
toxand threshold voltage (Vth), the leakage power increases
exponentially and limits IC yield for low power applications at
65 nm technology and below . On the other hand, because
delay is inversely proportional to the dynamic power, the best
chips from the timing viewpoint may dissipate unacceptable
power. Therefore, industries and designers are concerned about
the trade-off between performance, power and yield (PPY)
Statistical timing analysis has been investigated intensively
in the last decade , but there has been little research on
power variation. Power includes static and dynamic compo-
nents. It is a critical parameter affecting packaging, cooling,
battery lifetime and chip reliability. The static power (SP) is
induced by leakage current and includes subthreshold leakage
(Isub) and gate leakage (Igate); both increase significantly
with decreasing L, toxand Vth. The dynamic power (DP)
includes short circuit power and power dissipated by charging
and discharging of internal and external load capacitances. The
increase of process variation gives rise to more uncertainty in
L, toxand Vth, which are considered as the main culprits for
timing and power fluctuations ,. Although statistical
analysis of leakage power has been reported ,,,–
, similar investigations of DP have not been widely done
up to now. Moreover, the statistical power analysis by Monte
Carlo (MC) SPICE simulations is time-consuming and im-
practical for large scale designs. Therefore, a usable statistical
power analysis technique is needed.
In this paper, we present a statistical power analysis tech-
nique for nanoscale CMOS design. Variation in Vth (σVth)
is taken to represent intrinsic process variations and Vth
is assumed independent and Gaussian distributed, which is
acceptable for in-die analysis . SP and DP are statistically
analyzed by the proposed technique based on two cell libraries.
One is a standard cell library (SCL) written with mean powers
(µP) from MC simulations. µP of a design is extracted from
the SCL by gate-level analysis. The other library is called
the standard deviation library of power (SDLP), containing
standard deviations (σ) of SP (σSP) and DP (σDP) at specific
input transition times (tr/tf) and load capacitance (CL). σSP
and σDP of cells are extracted from the SDLP, and σP of a
design is calculated by statistically adding all the cells’ σSP
and σDP. The validity of the proposed technique is verified
by comparing with MC method on ISCAS benchmark circuits
at 35 nm.
II. POWER VARIATION OF CMOS CELLS DUE TO
A. INTRINSIC VARIATION MODELLING
The main sources of intrinsic variations are RDD, LER and
PSG for “bulk” MOSFETs with polysilicon gates . Sim-
ulations demonstrate that σVth induced by the three sources
is almost the same as the total σVthmeasured at 45 nm .
RDD results from fluctuations of dopant number and doping
profile in the device active region, which are hard to control
as the dopant number and gate area get smaller . It is found
that σVthfrom RDD has a power law relationship with doping
density and is inversely proportional to the square root of
gate area . LER is due to incident photon number variation
during lithography exposure, absorption rate and chemical at-
tributes of photoresist . It gives rise to significant L variation
at sub-50 nm. PSG has been identified as an important source
STATIC POWER VARIATION OF STANDARD CMOS CELLS
!A & !B
!A & B
A & !B
A & B
!A & !B
!A & B
A & !B
A & B
of intrinsic fluctuations, because of the diffusion along the
grain boundaries and penetration of dopants through the gate
oxide into the channel from the high doping regions in the
The Vthvariation from the above three combined sources
is assumed to be Gaussian , . In this work, variations
in Vthare used to represent the effects of intrinsic variations
on device characteristics. Simulation of power dissipations is
done by using σVth=30mV as an input parameter for 35 nm
MOSFET models . The BSIM4 models are extracted by
a 3D atomistic simulator .
B. STATIC POWER VARIATIONS
The power dissipated by a MOSFET in steady state is
known as static or leakage power, for which the dominant
source is the Isubformed by the diffusion of minority carriers
in the off state. Isubvaries exponentially with Vth, assuming
Leff, Weff and tox are constants . Fig. 1 shows the
dependence of SP on Vth for a CMOS inverter. SP at low
and high inputs is determined by the n- and p-MOSFETs,
respectively. It is reported that subthreshold leakage power
will reach up to 50% of the total power for mobile systems at
65 nm technology . Moreover, because of the exponential
dependence on Vth, SP is more affected by process variations.
At room temperature and n ≈ 1, a 30mV σVth results
in ∆Isub with almost the same value as the nominal Isub.
Increasing ∆Isubhas an adverse influence on power yield for
lower power products. Table I shows the µSP and σSP of
INVERTER, 2-input NAND and 2-input NOR for 10 000 MC
simulations with 30mV σVth. It is found that µSP and σSP
are approximately the same for the cells; this is consistent
with the prediction of equation (1). In addition, SP from a p-
MOSFET is larger than that from an n-MOSFET because I0P
is several times I0N from the definition. The SP difference
between the low and high input of INVERTER confirms the
C. DYNAMIC POWER VARIATIONS
Dynamic power dissipation occurs when a stimulus is
applied to the circuit irrespective of whether the output logic
changes or not and is composed of internal and switching
Fig. 1.The dependence of static power on Vthof 35 nm CMOS inverter.
power. The internal power dissipated within a cell includes
short circuit power (PSC) during the inputs transition proce-
dure as both n- and p-MOSFETs switch on simultaneously, and
the power consumed on charging and discharging the internal
load (Pint). The switching power (PSW) of a driving cell is
dissipated by the load capacitance at the output of the cell.
DP = PSC+ Pint+ PSW
All three components have a dependence on the input tr/tf;
PSC is also affected by device dimensions and Vth; Pint is
determined by cell properties; and PSW is influenced by CL.
In cell-based IC design, DP is extracted from two-dimensional
lookup tables characterizing DP at pre-specified tr/tfand CL.
To investigate the dependence of σDPon switching speed and
CLat constant σVthwhile ignoring fluctuations of L and tox,
MC simulations are done under different conditions. Fig. 2
shows the σDP of INVERTER, NAND and NOR gate with
(a) input slew and (b) CLvarying, data points are extracted by
10 000 iterations MC simulations. It is seen that the σDP are
affected by both tr/tf and CLfor all the cells. Therefore, we
propose to extract the σDP of cells from a newly generated
cell library written with the simulation data. This is described
in the next section.
III. STATISTICAL POWER ANALYSIS
We select σVthto reflect the intrinsic variations and ignore
fluctuations of L and toxfor demonstrating our SPA technique.
Firstly, the statistical analysis of SP for standard cells is done
by MC simulations, µSP and σSP (Table I) are obtained and
written to the SCL and SDLP, respectively. From gate-level
analysis, the probabilities of different static values (PS) can
be obtained. PS is determined by circuit configuration and
input waveforms. SP of a cell is the leakage powers of static
values multiplied by the corresponding PS.
µSPC= µSP1× PS1+ µSP2× PS2+ ···
SPC= (σSP1× PS1)2+ (σSP2× PS2)2+ ···
and (b) FO varying at σVth=30mV. NANDA(B), NORA(B): output transition
activated by input signals at input A(B).
σDPof INVERTER, NAND and NOR at 35 nm with (a) input slew
The µSP and σSP of a design is then calculated by,
µSPD= µSPC1+ µSPC2+ µSPC3+ µSPC4+ ···
Then, we characterize DP for the SCL and SDLP. The SCL
includes lookup tables of energy dissipations during input
transitions at different tr/tf and CL. The values are mean
energy dissipations obtained from MC simulations. DP is
affected by both the frequency (f) of input signals and the
switching activities of cells. The µDP of a cell is extracted
by gate-level analysis from the SCL, and the design’s µDP is
sum of that of all cell DP. The σ of energy dissipations from
MC simulations are written to the SDLP, so σDP of cells and
design can be extracted from it.
µDPD= µDPC1+ µDPC2+ µDPC3+ µDPC4+ ···
The total power and its variation of a design is obtained by
the sum of SP and DP of all cells,
µP= µSPD+ µDPD
Because the power values of the libraries are extracted by
MC method, accuracy of the proposed technique should be
comparable with transistor-level SPICE simulation.
IV. RESULTS AND DISCUSSION
First, the proposed SPA technique is used to analyse SP of
ISCAS benchmark circuits. Table II is the statistical analysis
of SP by SPA and MC simulations. 10 000 iterations MC are
done at 30mV σVth without input stimulus. It is found the
maximum difference between the two methods in both µSP
and σSP is 2.15%.
Then, the SPA is applied to ICs with different input signals,
of which both SP and DP are involved. µ, σ of SP and
DP are extracted by the same procedure from the SCL and
SDLP, respectively. MC simulations are done by supplying the
same input stimulus. MC method simulates the total power
but cannot distinguish proportions of SP and DP. So, the
comparison of total power between the SPA and MC method
We analyse power variations of ISCAS-85 C432, a 27-
channel interrupt controller synthesized to 192 standard cells.
Table III shows comparisons between the results of the pro-
posed SPA and MC simulations. The powers are analysed at
different operating frequencies with different combinations of
input stimulus, which are selected randomly. The differences
in µPand σPbetween SPA and MC are several percent for all
selected inputs combinations. Fig. 3 shows power distributions
operating at 100MHz analysed by the SPA and MC method,
distribution of SPA is produced by assuming Gaussian and
using the extracted µ, σ. The distributions from the two
methods are close to each other in the figure, confirming the
validity of the SPA.
Fig. 3.Power distributions of ISCAS C432 at 100MHz.
In this work, we presented a SPA technique to analyse
both static and dynamic power. The proposed SPA technique
STATISTICAL ANALYSIS OF STATIC POWER FOR ISCAS BENCHMARK CIRCUITS BY SPA AND MC SIMULATIONS
COMPARISON OF POWER VARIATIONS OF ISCAS C432 BETWEEN THE PROPOSED SPA AND MC SIMULATIONS
extracts powers by extrapolating from cell libraries charac-
terized by Monte Carlo (MC) simulations. The standard cell
library (SCL) contains the mean values (µ) and the standard
deviation (σ) library of power (SDLP) includes the σ of static
and dynamic powers. µP and σP of cells in a design are
extracted by gate-level analysis from the SCL and SDLP,
respectively. µP and σP of a design is the statistical sum of
that of cells. Power variations of ISCAS benchmark circuits at
35 nm with 30mV of σVthare analysed by using the proposed
SPA technique and MC method; the errors of SPA compared
with MC are acceptable.
This work is supported by the Engineering and Physical
Sciences Research Council, United Kingdom under grant No.
EP/E002064/1. The transistor models were supplied by the
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