The SYNC Chip in the Electronics Architecture of the LHCb Muon Detector

Abstract

We present a custom integrated circuit, named SYNC, which plays a fundamental role in the time alignment of the LHCb Muon Detector and consequently in the trigger performance. The SYNC is realized in IBM 0.25 μm technology, using radiation-hardening layout techniques. SYNC receives data from the muon detector front-end electronics synchronizing them with the 40.08 MHz LHC clock. The data are tagged with the correct Bunch-Crossing identifier, output to the trigger system and stored in internal memories. The chip integrates 8 time to digital converters with a resolution up to 1 ns to measure the time phase of the input signals with respect to the system clock period. A histogram block can build real time spectra from the TDCs output. A I²C interface is implemented to configure and control the device, while a JTAG interface is integrated for boundary-scan purpose. We describe the circuit architecture, its internal blocks and its main modes of operation. Measurements performed on final prototypes are also reported.

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The SYNC Chip in the Electronics Architecture of
the LHCb Muon Detector
Sandro Cadeddu, Vincenzo De Leo, Caterina Deplano and Adriano Lai, Member, IEEE
Abstract—We present a custom integrated circuit, named
SYNC, which plays a fundamental role in the time alignment
of the LHCb Muon Detector and consequently in the trigger
performance. The SYNC is realized in IBM 0.25 µm technology,
using radiation-hardening layout techniques. SYNC receives data
from the muon detector front-end electronics synchronizing them
with the 40.08 MHz LHC clock. The data are tagged with the
correct Bunch-Crossing identifier, output to the trigger system
and stored in internal memories. The chip integrates 8 time
to digital converters with a resolution up to 1 ns to measure
the time phase of the input signals with respect to the system
clock period. A histogram block can build real time spectra from
the TDCs output. A I2C interface is implemented to configure
and control the device, while a JTAG interface is integrated for
boundary-scan purpose. We describe the circuit architecture, its
internal blocks and its main modes of operation. Measurements
performed on final prototypes are also reported.
Index Terms—Application specific integrated circuit, digital
circuit, time to digital conversion, I2C, JTAG, EDAC.
I. INTRODUCTION
S
experiment [1] at the CERN LHC. The LHCb Muon Detector
has to detect muons tracks with high transverse momentum as
a signature of a B meson decay. This information is crucial
for the first trigger level of the experiment, called ”level zero”
(L0) trigger.
The Muon Detector consists of 5 stations along the beam
axis and is based on 3-GEM (Gas Electron Multiplier) detec-
tors for the inner part of the first station and MWPC (Multi-
Wire Proportional Chambers) for the rest [2]. The L0 muon
trigger identifies a muon track looking for 5 hits, one per
station, pointing to the interaction point and in coincidence
in the same bunch crossing.
About 126,000 front-end channels are output from the
detector, while the trigger processor receives only about 26,000
read-out channels [3]. To minimize the number of signal
connections a logical reduction of the front-end channels
is performed on the front-end boards by an ASIC named
DIALOG [4] and by the Intermediate Boards (IB). The read-
out channels then go to the Off Detector Electronics (ODE) [5]
at the input of the ODE boards where the SYNC is placed. The
architecture of the electronics of the muon system is shown in
YNC is a custom integrated circuit dedicated to the Muon
Detector of the LHCb (Large Hadron Collider beauty)
Manuscript received March 17th, 2010; revised June 18th, 2010.
S. Cadeddu, C. Deplano and A. Lai are with the Istituto Nazionale di Fisica
Nucleare, Sezione di Cagliari, Cittadella Universitaria - 09024 Monserrato
(Cagliari) - Italy.
V. De Leo is with the Physics Department, University of Cagliari, same
site.
S. Cadeddu is the corresponding author (e-mail: sandro.cadeddu@ca.infn.it)
Fig. 1.Architecture of Muon system electronics.
Fig. 1. The SYNC implements the muon functions of the L0
stage [6].
The LHCb interactions have a bunched structure with a
possible Bunch Crossing (BX) every 25 ns, according to the
bunch crossing frequency of 40.08 MHz. The BX structure
has a period of 3564 cycles (LHC orbit) and it is character-
ized by a regular sequence of BX periods with and without
interactions [6]. Every 25 ns the L0 muon trigger receives the
complete binary map from the detector electronics along with
the associated bunch crossing (BX) identifier, which defines
the event time. Both the trigger and the read-out electronics
operate synchronously according to a pipeline architecture.
In order to reach the required trigger efficiency of 95% in
muon identification, which reflects to a requirement of 99%
detection efficiency per station, it’s crucial to tag each event
with the correct BX identifier (BXid). This means that all the
different contributions to signal delay must be compensated
before the detector information is sent to the trigger. The main
contributions to channel delays are due to the time of flight

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of the particles (up to about 20 ns between the first and the
last muon station) and the different cable lengths (10 m to
21 m) between front-end electronics on chambers and SYNCs.
These contributions produce a delay among different channels
of more than 2 BX and must be compensated. Moreover the
specific time resolution of the detector and associated front-
end electronics has a typical R.M.S. of 3 ns to 4 ns. Therefore
to avoid that the tails of the time distribution are assigned to
a wrong BX and to reach the required trigger efficiency, it is
necessary to center each front-end signal inside the 25 ns time
window with a precision of about 2 ns.
The Muon Detector time alignment is performed acting both
on DIALOG and SYNC [7].
II. TECHNOLOGY CHOICE
Several solutions were studied before deciding to implement
the SYNC chip as an ASIC. In 2000, when the study was
carried out, the possible alternative to an ASIC implementation
were the FPGA families of XILINX (VirtexE), Altera (APEX
20kE) and Actel (MX antifuse or ProAsic 500k). Parameters
addressing the choice were:
1) Degree of feasibility of SYNC for technology perfor-
mances,
2) Behavior under radiation,
3) Impact on system cost.
All functionalities required to SYNC were feasible in both
XILINX and Altera devices, but they were ruled out due to
their behavior under radiation. Dedicated tests demonstrated
that with FPGA technologies at least a couple of Single
Event Upsets per minute were to be expected in the system
[8]. The Actel anti-fuse devices showed a good resistance
to radiation effects, but they were incompatible with the
functional requirements to the SYNC chip, in particular with
respect to the lack of RAM, needed to implement the L0
memories.
The system cost was another advantage for the ASIC solu-
tion. For the Muon Detector other two ASIC were developed,
both in IBM 0.25 µm technology: DIALOG and CARIOCA
[9]. They were to be installed on the muon detector chambers
and therefore they were to be developed as ASICs. Including
the SYNC chip on the same production wafer of the other
two chips made transparent the engineering and production
run costs of the SYNC chip itself.
The possibility to adapt to the SYNC circuit the DLL block
(see below Section IV) already developed for DIALOG, was
another important point in favor to the ASIC choice. Last
but not least, the development of an ASIC gave important
advantages at the system level in terms of compactness (192
channels housed in one 6U VME board), reliability (all the L0
functionalities in one device) and power consumption (smaller
number of overall components) .
III. ARCHITECTURE AND CIRCUIT DESCRIPTION
SYNC is housed on the ODE boards in number of 24 chips
per board. In the whole Muon apparatus there are 152 ODE
boards for a total of 3648 SYNC.
The architecture of the SYNC chip is shown in Fig. 2.
Fig. 2.Internal architecture of SYNC.
Eight LVDS signals are received from eight detector chan-
nels. Each SYNC channel is equipped with a Time to Digital
Converter (TDC) measuring the input signal phase with respect
to the 40.08 MHz clock with a resolution of 1.56 ns (1/16 of
the reference clock). The measured phase can be used in the
histogram block to build histograms of incoming signals on-
the-fly . After the TDCs, the different channels are aligned
together using small pipelines, one for each channel, so that
the same BXid can be assigned to them. The BXid is generated
inside the chip by a 12-bit counter that can be preloaded with a
programmable value to achieve the BXid synchronization. The
data and the associated BXid are then sent to the trigger via an
optical link through the GOL chip [10]. The same information
is stored onto a pipeline memory waiting for the L0 trigger
response in order to be acquired or discarded. Information
stored in memories are encoded using a hamming code to
protect them against Single Event Upsets due to radiations
(see Section VIII).
If data are accepted by the trigger, they are extracted from
the pipelines and stored into a derandomizer memory, along
with additional information, to be sent to the next DAQ
electronic stage.
Several tools for testing purpose are also implemented inside
the device in order to check and monitor its operation, and in
particular all the connections between SYNC and the other
parts of the readout chain.
A high level of programmability is foreseen to satisfy all re-
quirements when installed in the Muon apparatus. The control
of these parameters is allowed through an I2C interface [11].
A JTAG interface is also implemented for boundary scan

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Fig. 3.SYNC layout
purpose.
The SYNC chip layout is shown in Fig. 3. Its main
characteristics can be found in table I.
TABLE I
SYNC CHARACTERISTICS.
Pin97
Voltage
Power Cons.
Area
Package
2.5 V
∼ 130mA
4x4 mm2
TQFP 14x14 100 pins
IV. CUSTOM TDC
The TDC integrated on SYNC is the main block for the time
alignment purpose. A conceptual scheme is shown in Fig. 4.
It is based on a classic scheme with a tapped delay line
controlled by a DLL, which is formed by a Phase Detector, a
Charge Pump and a Voltage Controlled Delay Line (VCDL)
[12], [13]. The VCDL consists of a cascade of 16 delay units as
shown in Fig. 5. Control voltage Vctrl(see below) regulate the
current flowing through the cascaded inverters, changing the
rising and falling time and thus the timing from in to out. The
DLL reference clock is the system LHC clock at 40.08 MHz.
The VCDL output is monitored by a Phase Detector circuit
which verifies its phase with respect to the reference clock. The
Phase Detector drives the Charge Pump circuit to change the
control voltage Vctrlin such a way to reduce the phase shift
between the master clock and the VCDL output. This process
is repeated until the two signals are perfectly in phase.
In our TDC application, the VCDL is used to generate
sixteen delayed 40.08 MHz clocks, starting from the chip
master clock, each one delayed with respect to the previous
one by 1.56 ns. When a signal arrives, it strobes the values
Fig. 4.Conceptual scheme of the SYNC TDC.
of the 16 delayed clocks into 16 registers and their output is
encoded into 4 bits, being the number corresponding to the
measure of the signal arrival time. The output of the encoder
is clocked by the master clock to be synchronized with the
rest of synchronous circuits. This information is what we call
Fine Time. With this synchronization scheme, setup timing
violations could arise for signals arriving in the last TDC step
(1.56 ns). Their impact on time measurements is maximum
in a not yet synchronized system while is lowered below the
10−5level in a time aligned system with the incoming signal
well inside the clock cycle.
The circuit is able to process a signal every master clock cy-
cle. Fig. 6 shows the TDC phase measurement compared with
the same measurements performed by a LeCroy SDA6000
6 GHz oscilloscope.
V. HISTOGRAM FACILITY
The time distributions of the muon detector signals are built-
up inside the SYNC chip in a dedicated block. This allows
accumulating very high statistics without passing through
the normal data acquisition, thus studying the detector time
performance at a very early stage of commissioning when
collision and physics data are not yet available. As the Fine
Fig. 5.Conceptual scheme of the Delay Unit cell.

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Fig. 6.
measurement are in agreement with the oscilloscope ones within the error
range.
TDC Phase measuring w.r.t. oscilloscope. All the SYNC TDC
Time (FT) information is stored on the pipeline memories and
available in the data acquired on disk, the internally built time
histograms are also a powerful crosscheck tool to monitor
the correct operation of the read-out chain at different stages.
In the SYNC chip a single histogram block is implemented
serving all the input channels, one at a time.
A block diagram is shown in Fig. 7. It consists of sixteen
24-bit counters that are addressed by the FT value. When a
new signal is detected, the counter selected from its FT is
incremented by one unit. When one of the counters reaches
the maximum value (i.e. 224-1), all the histogram counters are
disabled.
As the FT information is stored on the pipeline memories
and is retrieved when a trigger accept signal is received,
it is possible to configure the histogram block to build FT
histograms using data accepted by the trigger instead of the
”pre-triggered” ones.
Alternatively a histogram of incoming signals with respect
to the first 16 BXid of the LHC orbit can be built-up. In this
mode the counter to be incremented is selected from the four
Fig. 7.Time histogram builder scheme.
least significant bits of the BXid when the others are equal to
zero. The BXid histograms can be built for a single channel
or for all channels OR-ed together.
VI. TRIGGER INTERFACE
At 40.08 MHz and for each input channel, a single bit is
transmitted (Hit/no-Hit) to the L0 Muon Trigger electronics
[14], [15] for a total of 8 bits of information. Along with
this binary information, the two least significant bits of BXid
are sent. The data output are serialized by the GOL chip and
transmitted through an optical link.
The GOL is used in Fast Ethernet Mode, where each byte is
converted into a 10-bit word for transmission using a 8B/10B-
encoding [16]. The data Path is 32-bit wide. Two signals,
internally generated by SYNC, are used for data transmission
control: tx en and tx er (see Table II).
TABLE II
GOL CHIP IN 8B/10B MODE.
tx er
0
0
1
1
tx en
0
1
0
1
Encoded 10 bit output
IDLE(<K28.5 >, <D5.6 >, <K28.5 >, <D16.2 >)
Normal data from din<31:0 >
Carrier Extend(<K23.7 >)
Transmit error propagation (<K30.7 >)
tx en is asserted when data associated with the BXid zero
are output and deasserted one up to 16 cycles before the end
of the LHC orbit in order to re-initialize and re-synchronize
the optical link.
As GOL accepts 32 input bits and SYNC outputs 8+2 bits
for each event, from 2 to 4 SYNCs are connected to one
GOL. Therefore it is fundamental that all the data sent to
the same GOL are related to the same BXid event. To
allow this synchronization, a programmable pipeline buffer is
implemented on the trigger data output flow.
A. Test tools
Several facilities are implemented on SYNC to test and
monitor the optical link performance between SYNC and the
L0 trigger electronics. All the tests can be performed through
the slow control via I2C interface.
Three test modes are provided:
1) Static Test
2) Circular Test
3) Pseudo Random Pattern Generator
In Static Mode the tx en and tx er are managed setting the
selected values in a dedicated configuration register. Instead
of the input data and the related BXid, a pattern stored into a
configurable register is sent.
In Circular Mode the data output to GOL and its BXid bits
are set as in the previous test, but the GOL control signals
tx en and tx er are toggled at the master clock frequency of
40.08 MHz by a 2-bit counter with the tx en as least significant
bit.
In Random mode, linear feedback shift registers are used
to generate a pseudo-random sequence [17]. They consist of a

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simple eight bit shift register where some outputs are X-ORed
and fed back to the input as shown in Fig. 8. The outputs to
be X-ORed are chosen to obtain the maximal sequence length
of 255 words, according with the primitive polynomial
1 + x4+ x5+ x6+ x8
(1)
A sequence of 256 words is generated starting from a pro-
grammable seed that is the first and last sequence word. The
seed must be different from zero. In this mode, the full 256-
word sequence is transmitted at 40.08 MHz followed by 4
IDLE characters to keep the optical link synchronization.
VII. DATA ACQUISITION INTERFACE
While a binary information is sent to the trigger, the full
FT information is sent to the DAQ for events accepted by the
trigger. For each SYNC input channel, the four FT bits are
stored, with the convention that a zero means ”no Hit”, while
in case of a Hit with FT equal to zero, it is forced to one.
This means that the histogram bin corresponding to FT equal
to one has entries due to contributions both from FT equal
to zero and one. The full information stored in the pipeline
memories at 40.08 MHz includes the FT value for each input
channel (32 bits) plus the 4 least significant bits of the BXid
associated, for a total of 36 bits.
The pipeline memories are based on a 128x27 bits DPRAM
developed at CERN [18]. Four blocks are used to implement
a memory of 256x64 bits. It works as a circular memory
and the starting write and read addresses can be set via I2C,
determining the data latency inside the RAM.
Before data are written into the memories, they are coded
using a Hamming code algorithm [19]. Using this approach,
we add 6 parity bits, which are added in the position power of
2 (i.e. positions 1,2,4,8,16,32), while the remaining positions
are for data. Each parity bit is calculated over a portion of
data bits. Adding in the position zero an extra even parity
bit calculated over all the other bits (data as well as parity
bits) a double error detection capability is achieved. When
data are read from memory, an EDAC block checks the parity
again according to the same grouping as at the input, this
time including also the parity bit itself. The binary word
C=C32,C16,C8,C4,C2,C1gives the position of the bit in error,
(if any). Checking also the overall parity C0 of the output
word (data plus parity bits, included the one in position zero)
we can have the following four cases:
1) C=0 and C0=0: No errors
2) C=0 and C0=1: Errors occurred in bit zero
Fig. 8.Pseudo-Random Pattern Generator scheme.
3) C̸=0 and C0=1: A single error occurred in position C
that can be corrected.
4) C̸=0 and C0=0: A double error occurred that is detected
but cannot be corrected.
A flag output by the EDAC block signal the detection of error
and a second flag indicates if these were corrected or not.
When a L0 accept is received from trigger, data are extracted
from memory and stored into a derandomizer together with
other related information: the flags output from the EDAC
block and the 4 least significant bit of an Event Counter. The
Derandomizer is realized using 2 other 128x27 bit DPRAM
blocks, used as a FIFO of 128x56 bits. Also data stored
into the derandomizer are protected with a Hamming code
generator at the input and an EDAC block at the output.
Data from derandomizer are read-out divided in two 32-bit
words.
A. Test tools
A tool to test the DAQ read-out interface is developed. In
this mode the derandomizer is filled using a 32-bit pattern
stored on configuration registers instead of the fields normally
occupied by the FT information. The nthword stored in the
derandomizer differs from the nth-1 word by reversing second
and first bytes, as well as fourth with third bytes.
VIII. SEU PROTECTION
SYNC is realized using specific layout techniques (enclosed
gate structures) [20], [21] suitable to increase the device
radiation resistance. This technique applied to the IBM 0.25
µm technology has been proved to resist up to tens of Mrads
without significant performance loss [22], [23]. The highest
dose to be sustained in the Muon system front-end is around
1 Mrad in 10 LHC years, in the inner part of the first station,
while in the area where SYNC is installed the dose foreseen
is some Krad [24].
A special care should be spent about the problem of Single
Event Upsets (SEUs), which is expected to be relevant at the
radiation level present in the SYNC installation zone.
SEUs depend on particle rates rather than accumulated dose.
They normally appear as transient pulses in logic or support
circuitry, or as bit-flips in memory cells or registers. They
corrupt the configuration data, the data itself and the normal
operation of state machines. These are ”soft” bit errors in the
sense that a reset or reprogramming of the device restores
normal behavior.
The solution adopted on SYNC is to use the Triple Mod-
ular Redundancy for all the chip registers. Every register in
counters and Final State Machines is split into three registers
where the same bit is stored. A logic inputs the three flip-flop
outputs performing a majority-OR (two out of three).
A special care is given to the configuration registers where
the information stored is in some sense ”static”. In this
case, together with the Triple-Voted technique, an auto-refresh
system is implemented. The output of the three registers is
continuously monitored by the logic and in case one over
three is different, the majority-OR output is used to restore the

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register with the wrong value. This system is able to correct
a SEU event in about 2 ns.
Tests under radiation were performed on chip DIALOG, that
uses the same technology and for which the same solutions
against SEU were adopted. Resistance against accumulated
dose was done integrating a total dose of 1 Mrad without any
significant loss in performance, while SEU tests were done at
the Paul Sherrer Institute of Zurich with a 250 MeV proton flux
of 6·108cm−2s−1collecting a fluence of 1013·cm−2protons.
From these tests a negligible cross section per single register
was found [4]. Assuming the same cross section per register
also for SYNC, and considering that SYNC is installed on
the detector side where the fluence is estimated 3 orders of
magnitude lower than for DIALOG [25], the probability to
have an effective SEU is practically zero.
IX. PRODUCTION TESTS
A total of 3648 SYNC are needed to fully equip the LHCb
Muon Detector. Including 20% of spares, the required number
of SYNC chips is 4400.
Due to this amount of chips, a complete automatic test over
all the production is mandatory.
Several tests were implemented:
1) Continuity test: a small current is applied to a pin
while all the others are connected to ground to verify
continuity between the tester and the internal die. This
test can also spot shorts between adjacent pins and
between GND/VDD.
2) Leakage test: it is indicative of ”higher process defect
density” and ”higher than expected leakage” at the IO
pads, which can cause logic functionality and bus speed
problems.
3) Power consumption analysis, both static and dynamic,
are good meters of process defect density.
4) GoNoGo test is used to spot problems in the I/O signal
pads verifying the threshold levels are respected.
5) The Functional tests are performed using several test
vectors in order to verify the core logic is working as
expected. The vector generation is fundamental in order
to have the capability of detecting defect in the die under
test. The key parameter is the fault coverage that must
be as high as possible in order to have an acceptable
rejection of defected devices. The test vector set used
for the SYNC chip during production tests had a fault-
coverage around 98%.
A total of 5991 chips were produced. The yield was 81,96%,
i.e. 4910 chips were accepted. In Table III the test fault
distributions are reported.
The test procedure was executed by Microtest, a design,
testing and reliability center specialized in microelectronics
[26].
During post production tests, a non linear effect was dis-
covered in the TDC. Due to worst quality of the process
parameters of the production run, a DLL operation marginality
appeared in a relevant number of devices (about 30%). This
marginality causes the DLL being unable to rise the Vctrl
enough to set up the proper delay, resulting in a delay step
TABLE III
FAULT DISTRIBUTION FOR POST PRODUCTION TESTS.
TestFailed result
10.60%
5.90%
0.00%
0.64%
5.90%
Continuity
GoNoGo Vihl
GoNoGo Vohl
Static Power Cons.
Others
slightly higher than the correct one. The phenomenology and
consequences of this effect are analyzed in detail in [27].
This problem, once understood and kept under control, has
not prevented an accurate alignment of the system, as shown
in the following section.
X. COMMISSIONING AND USE IN APPARATUS
In the LHCb Muon apparatus 1,380 chambers with 7,632
Front-End boards are connected to 3,648 SYNCs with about
55,000 LVDS cables having length varying from 10 to 21
meters. Detector commissioning activities required big efforts
to be fulfilled and SYNC tools played a crucial role during
them.
The main commissioning activities where SYNC was in-
volved are connectivity tests and time alignment procedures.
A. Connectivity tests
Each ODE, housing 24 SYNCs, can input up to about
1,000 front-end channels distributed on up to 48 different
chambers and outputs up to 12 optical links (trigger side)
plus 1 more optical link (DAQ side). All these connections
are tested using tools implemented on SYNC and controlled
by PVSS programs [28] running on PCs placed outside the
cavern in a safe place with respect to the radiation.
Connections between Front-End boards and ODEs are veri-
fied using the SYNC histogram block as a counter. All the
front-end channels are muted on DIALOG except the one
under test for which a very low threshold is set to generate
noise, which is monitored by the SYNC histograms.
Eight hours are needed to complete the Connectivity test
of a complete ODE. Typical problems found during these
tests were in a wide spread of possibility: wrong PCB layout,
broken cables, connectors or pins, adjacent pins shortened or
floating, swapped cables. After each intervention, the test had
to be run again, in some case showing new problems.
Optical link connections between ODEs and trigger were
tested using the SYNC Static test Mode (see Section VI).
A unique pattern identifying the optical link was stored on
SYNC, sent continuously through the link while monitored
at the trigger side input. The same method was used for
the test of DAQ optical link, by sending a pattern stored
on SYNC through the derandomizer/optical link (see Section
VII). Typical problems found during optical link test were
broken or misplaced fibers. Low power emission problem was
sometime found too.
After this procedure few unsolved problems are still there,
for a total of 21 SYNC channels masked (around 0.1% of

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Fig. 9.
Detector.
Pulse distribution scheme for the time alignment in the Muon
the total), while all optical links to L0 Trigger and DAQ are
working properly.
B. Time Alignment using a pulsing system
As soon as the connectivity was checked and corrected, a
preliminary time alignment of the detector was performed in
order to have the better possible time alignment performance
when first collisions would arrived [29], [30]. This first align-
ment is done using a Pulse Distribution Module (PDM) [31],
that can output a synchronous pulse in a programmable bunch
crossing and at a fixed phase with respect to the LHC master
clock. The generated pulse is sent to the Front-end boards
through the Service Boards (SB) [32]. Cable length differences
in the Pulse distribution chain is compensated internally on
DIALOG using the knowledge of the lengths of the pulse
cables, in order to have the whole detector pulsed at the same
time. The pulse is input on the front-end amplifiers and follows
the normal data path arriving at the SYNC chips, where the
Time histograms are built. The pulse distribution scheme is
shown in Fig. 9. Front-end channels are time aligned one by
one, muting all of them except the one which must be aligned.
The thresholds are set to the maximum in order to avoid any
noise on the channel under test. A PVSS program controls all
the test flow, analyzing the histograms built from SYNC and
calculating the correction needed to align the signal.
Time alignment is performed in three steps. First the SYNC
input signal phase with respect to the LHC clock is measured
by the SYNC TDC building the histogram (FT). At the end the
corrections are applied on DIALOG to center the obtained dis-
tribution inside the BX period. Afterwards a BXid histogram is
build to verify that the pulse received by SYNC is tagged with
the same BXid set on the PDM generating the pulse (Coarse
Time, CT). Any difference is corrected modifying the SYNC
settings. Finally a check measurement (CTC) is performed to
verify that the time alignment is what expected after FT and
CT corrections, reporting possible misalignments still present.
In Fig. 10 a typical time alignment procedure output for
three different front-end channel is shown (one for each
column). The second peak visible sometimes in the CT and
Fig. 10. Three time alignment procedure outputs are shown. Each column is
relative to a different front-end channel. FT, CT and CTC measurement are
shown for each one.
CTC histograms is due to a bounce of the front-end amplifier
induced by the high analog pulse generated by the digital pulse
at its input. Typical corrections applied are comprised between
0 and 16 DIALOG delay steps for the FT, while for the CT
typical correction values are from 4 to 8 BX periods.
This procedure was executed over the whole apparatus. It
gave a very good starting time alignment when the system
was ready to acquire the first data of cosmics. The remaining
time corrections left from this procedure are due to offsets
that cannot be included into the pulse system: time of flight,
chamber response, time difference between the two Muon
detector sides and between Muon and the others detectors.
As soon as the muon system was ready to acquire cosmic
data, the time performance were analyzed, showing the ef-
fectiveness of time alignment performed at the early stage.
In Fig. 11 the time difference between Calorimeter and Muon
systems for forward cosmic tracks triggered by the Calorimeter
is shown. A time offset of 20 ns was found (upper plot)
and corrected (lower plot), demonstrating the pulse alignment
was good except for an offset. At the end of time alignment
procedure the resolution obtained is within 1 ns.

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Fig. 11.
Calorimeter before (upper) and after (below) time offset correction.
Forward cosmic track time at Muon for event triggered by
XI. CONCLUSION
An integrated circuit for the LHCb muon detector level-0
electronics was designed. This device is fundamental for the
detector timing alignment as well as to guarantee the trigger
efficiency required. Eight TDC’s are implemented allowing
the analysis of time performance and the calculation of time
corrections.
A special care was used to protect registers and RAM
contents against Single Event Upsets (SEU), using Triple
redundancy for registers and Hamming code for RAM.
In total more then five thousand chip were produced and
tested and about four thousand of them are mounted inside
the LHCb cavern.
During the Muon System commissioning, SYNC features
as TDC, histogram block and test tools for the optical links
have been fundamental to make the Muon System ready for
first collisions and physics data.
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