BD180LV ? 0.18 ?m BCD Technology with Best-in-
Class LDMOS from 7V to 30V
Kwang-Young Ko, Il-Yong Park, Yong-Keon Choi, Chul-Jin Yoon, Ju-Hyoung Moon, Kyung-Min Park,
Hyon-Chol Lim, Soon-Yeol Park, Nam-Joo Kim, Kwang-Dong Yoo and Lou N. Hutter
Analog Foundry Business Unit
Bucheon, South Korea
Abstract? 0.18?m BCD technology with the best-in-class
nLDMOS is presented. The drift of nLDMOS is optimized to
ensure lowest Rsp by using multi-implants and appropriate
thermal recipe. The optimized 24V nLDMOS has BVDSS=36V
and Rsp=14.5 m??mm2. Electrical SOA and long-term hot
electron (HE) SOA are also evaluated. The maximum operating
voltage less than 10% degradation of on-resistance is 24.4V.
Power management area is one of the highly growing
markets in the semiconductor industry. Recently BCD
(Bipolar-CMOS-DMOS) technology has been widely used
for various applications having large logic contents with
power management functions [1-2]. As more logic contents is
merged with power function in one chip, designers want BCD
process to have more and more dense logic such as 0.18um or
by adapting more dense technologies but the size of the high-
voltage devices can not be easily reduced due to the fact that
the given breakdown voltage needs a resistive area that can
sustains high voltage in the off-state. The higher voltage they
use, the bigger the resistive region is needed. We have a
trade-off between the breakdown voltage (BV) and the on-
resistance. In addition, efforts to reduce the on-resistance
would be a conflicting reverse direction for the reliability .
Therefore, we have to not only design the LDMOS to have
very good Rsp (specific on-resistance) at a given BV but also
satisfy reliability requirements. In this paper, we present the
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technology with optimized LDMOS from 7V to 30V. The
optimized LDMOS transistors have best-in-class Rsp and
good reliability characteristics as well.
Starting material is a p-epi on P+ substrate. NBL (N+
Buried Layer) is formed on it using Sb (antimony) implants.
NBL is used for vertical NPN transistor (collector), high-side
LDMOS, and isolated devices. Then, the p-type epitaxial
layer, with an appropriate doping concentration and a
thickness, is grown on NBL. In the process, 5V NWELL and
5V PWELL are used for body and drain of the DE (Drain-
Extended) CMOS. For the nLDMOS optimization, we used
dedicated NDT mask to form drift regions. Fig. 1 shows the
cross-sectional view of the 24V nLDMOS. We optimized the
drift region by using multi-implants of n-type and p-type
dopants at the same masking step.
Source & Body
Source & Body
Fig. 1. Cross-sectional view of 24V nLDMOS. (a) Low-side nLDMOS
(b) High-side nLDMOS
Proceedings of The 22nd International Symposium on Power Semiconductor Devices & ICs, Hiroshima
The optimized dose and energy is very important to achieve
low on-resistance and high breakdown voltage. In this
technology, the bottom p-type layer is used to ensure full
depletion of the n-type drift region so that we could increase
the doping concentration of the N-drift region. The p-body of
the LDMOS is formed by using double diffusion technique.
The p-body has very short channel length and can achieve
high transconductance and the current handling capability.
As shown in Fig. 1a, low-????? ??????? ???????? ?????
NBL (N+ Buried Layer) underneath. The source of the low-
side nLDMOS should be the same potential as the p-epi
(substrate). Otherwise, the high-side nLDMOS, as shown in
Fig. 1b, has a NBL which can prevent from the depletion of
the drift region when the source tied to the load. Fig. 2 shows
the simulated structure and impact ionization rate (Fig. 2a)
and the equipotential lines at breakdown (Fig. 2b). The
simulated breakdown voltage is 42V and the impact
ionization rate is highest at the side of STI near the gate. The
doping concentration of the bottom p-type region is very
important to ensure full depletion at breakdown. In addition,
the overlap spacing between N-drift and STI edge strongly
affects the Rsp and the breakdown voltage.
Fig. 2. Simulated LDMOS structure. (a) impact ionization rate and (b)
equipotential lines at breakdown (BV=42V).
Fig. 3 shows the IDS-VDS and breakdown characteristics
for the 24V nLDMOS which is measured by HP4156
semiconductor parameter analyzer. The width of 42 ?m was
used for the measurement and the VT of 1.0V was obtained.
The IDS-VDS curve shows very stable characteristics up to
27.5V and the actual off-state and on-state breakdown
voltages are 36V and 33V, respectively. The on-resistance is
measured at VGS=5.0V and VDS=0.1V. The specific on-
resistance (Rsp) for this 24V nLDMOS is 14.5 m??mm2,
which is the lowest value in the industry.
Fig 3. Experimental on-state IDS-VDS characteristics for 24V nLDMOS
(Width=42 ?m and VT=1.0V)
In the previous 0.18 ?m BCD technology, we had a 24V
LDMOS with Rsp of 28.9 ???mm2. Therefore, the new 0.18
?m technology can shrink 50% of the power transistor area.
Fig. 4 shows the trade-off characteristics between the
breakdown voltage and the specific on-resistance. Optimized
LDMOS in BD180LV process show the lowest Rsp value
compared to the previous publications.
Fig. 4. Trade-off characteristics between the breakdown voltage and the
A reliability of LDMOS becomes more and more
important as the Rsp optimization advances . Firstly, we
measure the electrical SOA, which is very short term SOA
measurement. The LDMOS is measured by using Barth TLP
system with pulse width of 100 ns and the rising time of 10 ns.
As shown in Fig. 5 the TLP result shows very robust I-V
characteristics with VDSup to 30V and gate electric field up
to 4.0 MV/cm. In addition, the I-V curve shows rectangular
shape of electrical SOA, which means the drift region is very
To further evaluate the reliability for this device, we
measured the degradation of the parameters when the high-
voltage stress is applied for a long time (up to 100,000 sec).
Fig. 6 shows the percentage of parameter drift of the worst-
case parameter (Id,lin) at various stress biases such as VDS=27,
28.5, and 32V at maximum gate bias of 5.5V. Fig. 7 shows
the extrapolated lifetime estimation as a function of inverse of
stress voltage. We measured several parameters such as drain
saturation current, on-resistance, and VT. The on-resistance
was the worst case parameter in the stress measurement. Fig.
7 shows that the degradation of on-resistance is less than 10%
for 10 years when the device is used at maximum operation
voltage of 24.4V.
Fig. 5. TLP I-V characteristics for the 24V nLDMOS (Width=42 ?m,
Threshold voltage VT=1.0V). The I-V curves are measured by Barth
transmission line pulse (TLP) system with pulse width of 100 ns and the
rising time of 10 ns.
Fig. 6. Worst-case bias stress (VGS=5.5V, VDS=27, 28.5, 32V)
degradation for linear-region IDS of the 24V nLDMOS.
Fig. 7. Lifetime estimation for the 24V nLDMOS.
The BD180LV process has variety of components such as
foundry compatible 1.8V and 5V CMOS logic devices,
vertical NPN and lateral PNP bipolar transistors, 5.6V Zener
diode, 2 K?/sq. high sheet rho resistor, and 1.8 fF/?m2 MIM
capacitor. An isolated 1.8V and 5V CMOS are also available
and the NBL and HVNWELL are used for isolation guard
ring. In addition, we provide drain-extended (DE) CMOS
from 7V to 30V for the high voltage circuitry. As a main
power device, the process has low-side and high-side
nLDMOS devices from 7V to 30V. The key electrical
specifications are summarized in Table 1.
TABLE 1. KEY ELECTRICAL SPECIFICATIONS FOR CMOS, BIPOLAR,
DIODE, PASSIVES, AND EEPROM.
Poly High Rs
Poly Med. Rs
Capacitor ?????????????2]BV [V]
MIM 1.8 21
1 10100 1000
(5V, 10 msec)
(-5V, 10 msec)
Fig. 8. Endurance test results (a) and cell VT characteristics (b) for the single-
A single-poly EEPROM is often used for trimming purpose
with few program/erase cycles in power management ICs.
The BD180LV provides a single-poly EEPROM without any
change and additional mask from the baseline process. Fig. 8
shows the endurance test results and the program/erase cell
VT characteristics for the single-poly EEPROM. A floating
poly forms the gate of NMOS and the top plate of the
coupling capacitor. The PWELL of NMOS is isolated by
HVNWELL and NBL from the PWELL of coupling capacitor.
Because the PWELLs are isolated, we can use +/- 5.5V for
programming and erase of the cell. Therefore, they can build
a periphery to drive the EEPROM by using only 5V CMOS
logic circuit. Thus, the IP size can be reduced due to the fact
that there is no need of high-voltage transistor for driving the
The new BCD technology with very low Rsp LDMOS was
introduced. The DC and reliability characteristics for the 24V
LDMOS were discussed. The 24V LDMOS showed
BVDSS=36V and Rsp=14.5 m??mm2, which are the best-in-
class Rsp performance in the industry. For reliability, we
measured electrical SOA and hot electron (HE) SOA. The
extrapolated lifetime showed that the maximum operation
voltage less than 10% degradation of worst case parameter is
The authors would like to thank Device Engineering Team
for TCAD simulation as well as Quality and Reliability
Assurance Team for HE-SOA measurement and lifetime
 I. Y. Park et al., ?BD180 ? a new 0.18 ?m BCD (Bipolar-CMOS-
DMOS) technology from 7V to 60V,?Proc. of ISPSD, pp. 64-67, 2008.
D. Riccardi et al., ?BCD8 from 7V to 70V: a new 0.18 ?m technology
platform to address the evolution of applications towards smart power
ICs with high logic contents,?Proc. of ISPSD, pp. 73-76, 2007.
K. Shirai et al., ?Ultra-low on-resistance LDMOS implementation in
0.13 ?m CD and BiCD process technologies for analog power ICs,?
Proc .of ISPSD, pp. 77-79, 2009.
S. Pendharkar et. al., ?7 to 30V state-of-art power device
implementation in 0.25 ?m LBC7 BiCMOS-DMOS process
technology,?Proc. of ISPSD, pp. 419-422, 2004.
??? ??? ??????? ??????? ?????????? ????? ? a new frontier in LDMOS
?????????Proc. of ISPSD, pp. 1-8, 2002.