Conference Paper

BD180LV - 0.18 μm BCD technology with best-in-class LDMOS from 7V to 30V

Analog Foundry Bus. Unit, Dongbu HiTek, Bucheon, South Korea
Conference: Power Semiconductor Devices & IC's (ISPSD), 2010 22nd International Symposium on
Source: IEEE Xplore

ABSTRACT 0.18μm BCD technology with the best-in-class nLDMOS is presented. The drift of nLDMOS is optimized to ensure lowest Rsp by using multi-implants and appropriate thermal recipe. The optimized 24V nLDMOS has BVDSS=36V and Rsp=14.5 mΩ-mm2. Electrical SOA and long-term hot electron (HE) SOA are also evaluated. The maximum operating voltage less than 10% degradation of on-resistance is 24.4V.

1 Follower
 · 
594 Views
  • [Show abstract] [Hide abstract]
    ABSTRACT: This paper reviews the technology trends of BCD (Bipolar-CMOS-DMOS) technology in terms of voltage capability, switching speed of power transistor, and high integration of logic CMOS for SoC (System-on-Chip) solution requiring high-voltage devices. Recent trends such like modularity of the process, power metal routing, and high-density NVM (Non-Volatile Memory) are also discussed. Power management is becoming highly growing market in semiconductor industry. A recent market survey results show that the total power management semiconductor is expected to grow with 15.5% for the next five years. And the future growth of power management market is mainly driven by mobile computer market, infrastructure replacement, alternative energy market, and improving efficiency of existing electronics. BCD (Bipolar-CMOS-DMOS) technology is the best solution for modern power management IC in various applications addressed above. The typical BCD technology offers low voltage logic CMOS transistors, high-voltage CMOS transistors, bipolar transistors, resistors, capacitors, diodes, and power LDMOS (lateral double-diffused MOS) transistors in the same process. The compatibility of CMOS between BCD and log CMOS process is very important for the reuse of the existing IP, which customers take so much time to develop. Normally BCD process has the parasitic bipolar transistors which are good enough to make analog circuits like bang gap reference. A LDMOS is used as a main power switch so that the on-resistance is very important to reduce the power dissipation and the size of the die. Current typical feature size of the BCD is 0.35 μm and 0.18 μm which are relatively larger than that of the CMOS. This is due to the fact that the high-voltage operation of the BCD needs lower doping concentration of the substrate and the large dimension to sustain high breakdown voltage. The BCD technology is evolving to meet the recent market needs. In this paper, the key technical trends in BCD technology are reviewed in terms of voltage capability, switching speed of power transistor, process integration, CMOS density, and some specific options like thick copper metal, memory, and high precision passive components. The paper classifies the BCD technology with several categories: 1) high-speed BCD
    01/2011; DOI:10.1109/ICPE.2011.5944616
  • [Show abstract] [Hide abstract]
    ABSTRACT: This paper presents BCD process integrating 7V to 70V power devices on 0.13um CMOS platform for various power management applications. BJT, Zener diode and Schottky diode are available and non-volatile memory is embedded as well. LDMOS shows best-in-class specific Ron (RSP) vs. BVDSS characteristics (i.e., 70V NMOS has RSP of 69mΩ-mm2 with BVDSS of 89V). Modular process scheme is used for flexibility to various requirements of applications.
    01/2012; DOI:10.1109/ISPSD.2012.6229062
  • Conference Paper: Interdigitated LDMOS
    [Show abstract] [Hide abstract]
    ABSTRACT: Novel Interdigitated LDMOS is experimented resulting in best in class RSP-BVDSS performance (21.8mΩ-mm2 with BVDSS of 47V) in comparison to published LDMOS. RSP improvement is made through additional current path by removing STI region in drift area. Breakdown voltage is maintained with lateral field plate effect from side of the current path. Proposed Interdigitated LDMOS satisfies reliability criteria (HCI, snap back) as 40V device. All of this is obtained without any process change.
    Power Semiconductor Devices and ICs (ISPSD), 2013 25th International Symposium on; 01/2013
Show more

Preview (2 Sources)

Download
55 Downloads
Available from