N-polar GaN-based MIS-HEMTs for mixed signal applications
ABSTRACT GaN-based transistors are attractive for the next-generation RF power and mixed signal electronics due to their high breakdown field and high carrier saturation velocity. III-N high electron mobility transistors (HEMTs) fabricated on the N-face of GaN are well-suited to address the problems of poor electron confinement and high ohmic contact resistance in the highly scaled transistors. At 4 GHz, N-polar metal-insulator-semiconductor (MIS)-HEMTs with a gate length of 0.7 μm exhibited a highest output power density (Pout) of 8.1 W/mm and a highest power-added efficiency (PAE) of 71%, while a Pout of 4.2 W/mm and a PAE of 49% were achieved at 10 GHz. A high speed N-polar MIS-HEMT fabricated with a gate-first self-aligned InGaN-based ohmic contact regrowth technology was characterized, demonstrating an ultra-low contact resistance of 23 Ω-μm and a state-of-the-art fT·LG product of 16.8 GHz-μm with a gate length of 130 nm.
- SourceAvailable from: Ashish Baraskar[show abstract] [hide abstract]
ABSTRACT: InGaAs is a promising alternative channel material to Si for sub-22 nm node technology because of its low electron effective mass (m*) hence high electron velocities. We report a gate-first MOSFET process with self-aligned source/drain formation using non-selective MBE re-growth, suitable for realizing high performance scaled III-V MOSFETs. A W/Cr/SiO2 gate stack was defined on thin (4 nm/2.5 nm) InGaAs/InP channel by an alternating selective dry etch technique. A 5 nm Al2O3 layer was used as gate dielectric. An InAlAs bottom barrier provided vertical confinement of the channel. An in-situ H cleaning of the wafer leaves an epi-ready surface suitable for MBE or MOCVD regrowth.Source/Drain region were defined by non-selective MBE regrowth and in situ molybdenum contacts. First generation of devices fabricated using this process showed extremely low drive current of 2 μA/μm. The drive current was limited by an extremely high source resistance. A regrowth gap between source/drain and gate was the cause for high source resistance. The gap in the regrowth was because of low growth temperature (400 °C). A modified high temperature growth technique resolved the problem. (© 2009 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)physica status solidi (c) 05/2009; 6(6):1394 - 1398.
Conference Proceeding: Technology development & design for 22 nm InGaAs/InP-channel MOSFETs[show abstract] [hide abstract]
ABSTRACT: Because of the low electron effective mass and the high resulting carrier velocities, we are developing InGaAs/InP MOSFETs for potential application in VLSI circuits at scaling generations beyond 22 nm. We will report device design, review gate dielectric growth processes, and describe in detail the development of process modules for fabrication of fully self-aligned enhancement-mode devices. Key design challenges include the effect of the low density of states upon drive current and the effect of the low carrier mass on vertical confinement. Target electrical parameters include ∼5 mA/μm drive current and ∼7 mS/μm<sup>2</sup> transconductance. Key fabrication challenges include formation of self-aligned N+ source and drain contacts with ≪ 15 Ω-μm and ≪ 1 Ω-μm<sup>2</sup> resistivity, and the formation and patterning of the gate metal and dielectric without damage to the thin underlying 4–6 nm channel layer.Indium Phosphide and Related Materials, 2008. IPRM 2008. 20th International Conference on; 06/2008
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ABSTRACT: Advanced III–V transistors require unprecedented low-resistance contacts in order to simultaneously scale bandwidth, fmax and ft with the physical active region [M.J.W. Rodwell, M. Le, B. Brar, in: Proceedings of the IEEE, 96, 2008, p. 748]. Low-resistance contacts have been previously demonstrated using molecular beam epitaxy (MBE), which provides active doping above 4×1019 cm−3 and permits in-situ metal deposition for the lowest resistances [U. Singisetti, M.A. Wistey, J.D. Zimmerman, B.J. Thibeault, M.J.W. Rodwell, A.C. Gossard, S.R. Bank, Appl. Phys. Lett., submitted]. But MBE is a blanket deposition technique, and applying MBE regrowth to deep-submicron lateral device dimensions is difficult even with advanced lithography techniques. We present a simple method for selectively etching undesired regrowth from the gate or mesa of a III–V MOSFET or laser, resulting in self-aligned source/drain contacts regardless of the device dimensions. This turns MBE into an effectively selective area growth technique.Journal of Crystal Growth 01/2009; 311(7):1984-1987. · 1.55 Impact Factor