A 17pJ/bit broadband mixed-signal demodulator in 90nm CMOS
Georgia Electron. Design Center, Georgia Inst. of Technol., Atlanta, GA, USADOI: 10.1109/MWSYM.2010.5518117 Conference: Microwave Symposium Digest (MTT), 2010 IEEE MTT-S International
Source: IEEE Xplore
This paper presents the first fully integrated mixed-signal demodulator incorporating ultra low-power 3mW 3Gsps 3-bit ADCs and a 2mW high-speed real-time digital signal processing in 90nm CMOS that requires neither external synchronization controls nor processing to demodulate up to 3.5Gbps binary phase-shift keying (BPSK) modulated signal. The demodulator is integrated with IQ mixers, 13GHz QVCO, frequency synthesizers and baseband AGC, for an overall power consumption of 60mW from a 1V supply. The entire demodulator chip occupies 1.275×1.19mm2 and enables error free demodulation up to 2.5Gbps and BER of 1E-09 up to 3Gbps. To the best of authors' knowledge, this demonstrates the maximum throughput at minimum power budget among all types of CMOS multi-gigabit demodulators.
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ABSTRACT: In this paper, a low-power high-speed fully integrated mixed-signal quadrature demodulator with an embedded multi-gigabit modem in 90 nm CMOS technology is presented. A wide dynamic-range automatic gain control (AGC) is implemented to avoid clipping distortion experienced by the baseband ADCs. By reusing the power detector circuit within the AGC, analog signal processor is introduced to recover OOK modulated signals up to 2.5 Gb/s for an additional power consumption of 7.5 mW. Integrated with ultra-low-power, 3 mW, 3 GS/s, 3-bit ADCs and high-speed digital modem, the system requires neither external synchronization controls nor processing to demodulate BPSK modulated signals up to 3.5 Gb/s and DBPSK modulated signals up to 1.3 Gb/s. The baseband modem incorporates a mixed-signal, timing-recovery loop to sample the symbols at the optimum SNR based on a high-speed Gardner timing-error detector for an additional power consumption of 14 mW. The analog front-end consists of IQ mixers, a 13 GHz QVCO, frequency synthesizers, and a baseband AGC for an overall power consumption of 52 mW. The entire receiver chip occupies an area of 1.275 × 1.19 mm<sup>2</sup>. To the best of authors' knowledge, this demonstrates the maximum throughput at the minimum power budget and highest level integration among all published wireless multi-gigabit, multi-mode, mixed-signal CMOS receivers.IEEE Transactions on Microwave Theory and Techniques 01/2011; DOI:10.1109/TMTT.2010.2084585 · 2.24 Impact Factor
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ABSTRACT: The paper proposes a CMOS 65 nm 24 GHz wide-band frequency synthesizer with programmability on acquisition speed and supply voltage for low power application in 60 GHz millimeter-wave (mmW) wireless transceiver. The role of mmW phase-locked loop (PLL) is significant for supporting 7 GHz bandwidth across the four channels in IEEE 802.15.3c. The PLL is introduced with consideration of system specifications, as well as the design of individual block. In order to maintain the dynamic behavior of a PLL, two control parameters of its loop transfer function are used for programmability, including the charge pump current and pole-zero position. A regulator is also adopted for supply noise suppression. The Voltage-Controlled Oscillator (VCO) covers frequency range from 24.2 to 29.3 GHz, with 19.1% tuning range. On top of the oscillator, a 1.2 V LDO (Low-Dropout Regulator) with 0.2 V dropout voltage is introduced to increase the immunity against low frequency noise fluctuation from supply. With the proposed structure, the PLL provides a loop bandwidth from 0.94 to 2.05 MHz. The phase margin is larger than 54° and the locking time can be adjusted 16% faster than nominal case. The VCO has better power supply rejection ratio (PSRR) of -48 dB, and Phase Noise of -94 dBc/Hz at 1 MHz frequency offset of 24 GHz.Journal of Circuits System and Computers 12/2012; 21(06). DOI:10.1142/S0218126612400099 · 0.25 Impact Factor
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