Article

3D Stacked Microprocessor: Are We There Yet?

Georgia Institute of Technology
IEEE Micro (Impact Factor: 1.81). 07/2010; DOI: 10.1109/MM.2010.45
Source: IEEE Xplore

ABSTRACT Editors' NoteWe live in a 3D world. It is hard to imagine a large city, such as New York City, with only single-level structures. There would be no skyscrapers, no mixed-use, no live-work. It would be a long walk (or drive) between everything, especially between dissimilar uses—all in all, very inefficient!Integrated circuits today are typically designed using single-level Manhattan geometries, nothing like the layout of the real city. In this prolegomenon, Gabriel Loh and Yuan Xie survey 3D integrated circuit technology, demonstrating the virtues, potentials, and challenges of applying three dimensions to future microprocessor designs and exploiting the locality and diversity of real-world Manhattan geometries.

0 Bookmarks
 · 
59 Views
  • [Show abstract] [Hide abstract]
    ABSTRACT: Fine grain 3D integration of commonly used components appears to be an attractive architectural solution. But finely partitioned, highly regular blocks face unique layout level challenges due to uneven scaling of Through Silicon Vias (TSVs) and circuit elements. We show that for high yielding TSVs and decreasing transistor sizes, the mismatch between the TSV dimension and the feature size affects the outcome of 3D design space exploration, especially for fine grain partitioned, highly regular microprocessor blocks such as SRAM registers and caches. For a 4-layer implementation of an SRAM register in 45nm technology, we show that improving the TSV yield from 20% to 90% requires layout modifications that worsen register's performance up to four times. Moreover, the same 4-layer register that performs three times as fast as its single layer equivalent at 20% yield becomes twice slower at 70% yield when layout effects are considered. We also explore some non-conventional physical design schemes for 3D architectural blocks in which performance deterioration is much slower even for very high TSV yields.
    Design Automation Conference (DAC), 2011 48th ACM/EDAC/IEEE; 01/2011
  • Source
    [Show abstract] [Hide abstract]
    ABSTRACT: Constant necessity of improving performance has brought the invention of 3D chips. The improvement is achieved due to the reduction of wire length, which results in decreased interconnection delay. However, 3D stacks have less heat dissipation due to the inner layers, which leads to increased temperature and the appearance of hot spots. This problem can be mitigated through appropriate floorplanning. For this reason, in this work we present and compare five different solutions for floorplanning of 3D chips. Each solution uses a different representation, and all are based on meta-heuristic algorithms, namely three of them are based on simulated annealing, while two other are based on evolutionary algorithms. The results show great capability of all the solutions in optimizing temperature and wire length, as they all exhibit significant improvements comparing to the benchmark floorplans.
    Neurocomputing 10/2014; · 2.01 Impact Factor
  • [Show abstract] [Hide abstract]
    ABSTRACT: Computer architectures have evolved to structures where communication has become an essential part of the system and most of it currently takes place inside the chip. The number of on-Chip cores and the available off-chip bandwidth is not growing at the same rate. This demands for the inclusion of more sophisticated memory hierarchies inside the chip to deal with off-chip latency and bandwidth problems in order to keep on improving performance. The exhaustion of Moore's law will accelerate the use of 3D-Stacked on-chip memory hierarchies to sustain the required scalability of forthcoming CMPs. For this class of systems' memory hierarchy, coherence protocol and interconnection network are two closely related components, but which are usually designed independently. In this work we will demonstrate that network components can be coupled to coherence protocol in order to extract significant performance benefits. Making use of a well-known snoop coherence protocol, we will present different network optimizations, better able to adapt to the communication requirements of this protocol. Evaluation results show that with minimal hardware changes, for some real applications, full system performance can be improved by up to 48%.
    Digital System Design (DSD), 2013 Euromicro Conference on; 01/2013

Preview

Download
0 Downloads
Available from