3D Stacked Microprocessor: Are We There Yet?
ABSTRACT Editors' NoteWe live in a 3D world. It is hard to imagine a large city, such as New York City, with only single-level structures. There would be no skyscrapers, no mixed-use, no live-work. It would be a long walk (or drive) between everything, especially between dissimilar uses—all in all, very inefficient!Integrated circuits today are typically designed using single-level Manhattan geometries, nothing like the layout of the real city. In this prolegomenon, Gabriel Loh and Yuan Xie survey 3D integrated circuit technology, demonstrating the virtues, potentials, and challenges of applying three dimensions to future microprocessor designs and exploiting the locality and diversity of real-world Manhattan geometries.
- SourceAvailable from: Mohamed M. Sabry[show abstract] [hide abstract]
ABSTRACT: This article explores the benefits and the challenges of 3D design and discusses novel techniques to integrate predictive cooling control with chip-level thermal-management methods such as job scheduling and voltage frequency scaling. Using 3D liquid-cooled systems with intelligent runtime management provides an energy-efficient solution for designing single-chip many-core architectures.IEEE Micro 01/2011; 31:63-75. · 2.39 Impact Factor
Conference Proceeding: Layout effects in fine grain 3D integrated regular microprocessor blocks.[show abstract] [hide abstract]
ABSTRACT: Fine grain D integration of commonly used components appears to be an attractive architectural solution. But finely partitioned, highly regular blocks face unique layout level challenges due to uneven scaling of Through Silicon Vias (TSVs) and circuit elements. We show that for high yielding TSVs and decreasing transistor sizes, the mismatch between the TSV dimension and the feature size affects the outcome of 3D design space exploration, especially for fine grain partitioned, highly regular microprocessor blocks such as SRAM registers and caches. For a 4-layer implementation of an SRAM register in 45nm technology, we show that improving the TSV yield from 20% to 90% requires layout modifications that worsen register’s performance up to four times. Moreover, the same 4-layer register that performs three times as fast as its single layer equivalent at 20% yield becomes twice slower at 70% yield when layout effects are considered. We also explore some non-conventional physical design schemes for 3D architectural blocks in which performance deterioration is much slower even for very high TSV yields.Proceedings of the 48th Design Automation Conference, DAC 2011, San Diego, California, USA, June 5-10, 2011; 01/2011
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ABSTRACT: This column examines how GPU computing might affect the architecture of future exascale supercomputers. Specifically, the authors argue that a system with slower but better-balanced processors might yield higher performance and consume less energy than a system with very fast but imbalanced processors.IEEE Micro 09/2011; · 2.39 Impact Factor