Article

3D Stacked Microprocessor: Are We There Yet?

Georgia Institute of Technology
IEEE Micro (Impact Factor: 1.81). 07/2010; 30(3):60 - 64. DOI: 10.1109/MM.2010.45
Source: IEEE Xplore

ABSTRACT Editors' NoteWe live in a 3D world. It is hard to imagine a large city, such as New York City, with only single-level structures. There would be no skyscrapers, no mixed-use, no live-work. It would be a long walk (or drive) between everything, especially between dissimilar uses—all in all, very inefficient!Integrated circuits today are typically designed using single-level Manhattan geometries, nothing like the layout of the real city. In this prolegomenon, Gabriel Loh and Yuan Xie survey 3D integrated circuit technology, demonstrating the virtues, potentials, and challenges of applying three dimensions to future microprocessor designs and exploiting the locality and diversity of real-world Manhattan geometries.

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    • "In fact, many-core system-onchip are so common that they usually equip phones we carry in our pockets. Despite the current high-level performance, silicon chip technology improvements do not stop, and they are currently moving from 2D to 3D chips [16]. Hence, problems considered already solved become more complicated and need new approaches. "
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    ABSTRACT: Constant necessity of improving performance has brought the invention of 3D chips. The improvement is achieved due to the reduction of wire length, which results in decreased interconnection delay. However, 3D stacks have less heat dissipation due to the inner layers, which leads to increased temperature and the appearance of hot spots. This problem can be mitigated through appropriate floorplanning. For this reason, in this work we present and compare five different solutions for floorplanning of 3D chips. Each solution uses a different representation, and all are based on meta-heuristic algorithms, namely three of them are based on simulated annealing, while two other are based on evolutionary algorithms. The results show great capability of all the solutions in optimizing temperature and wire length, as they all exhibit significant improvements comparing to the benchmark floorplans.
    Neurocomputing 10/2014; 150. DOI:10.1016/j.neucom.2014.06.078 · 2.01 Impact Factor
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    • "However, emerging 3D-stacked DRAM based on the Wide-IO standard [6] is a promising main memory alternative for future mobile devices for three reasons. First, reducing the need of IO drivers and interconnect compared to off-chip memories results in significant power savings [7]. Second, the excellent electrical characteristics of Through Silicon Via (TSV) enable the use of low-power CMOS transceivers, which save up to 98% of interface power [8]. "
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    ABSTRACT: The performance and power consumption of mobile DRAMs (LPDDRs) depend on the configuration of system-level parameters, such as operating frequency, interface width, request size, and memory map. In mobile systems running both real-time and non-real-time applications, the memory configuration must satisfy bandwidth requirements of real-time applications, meet the power consumption budget, and offer the best average-case execution time to the non-real-time applications. There is currently no well-defined methodology for selecting a suitable memory configuration for real-time mobile systems. The worst-case bandwidth, average-case execution time, and power consumption of mobile DRAMs across generations have furthermore not been investigated. This paper has two main contributions. 1) We analyze the worst-case bandwidth, average-case execution time, and power consumption of mobile DRAMs across three generations: LPDDR, LPDDR2 and Wide-IO-based 3D-stacked DRAM. 2) Based on our analysis, we propose a methodology for selecting memory configurations in real-time mobile systems.We show that LPDDR (32-bit IO), LPDDR2 (32-bit IO) and 3D-DRAM (128-bit IO) provide worst-case bandwidth up to 0.75 GB/s, 1.6 GB/s and 3.1 GB/s, respectively. We furthermore show for an H.263 decoder that LPDDR2 and 3D-DRAM reduce power consumption with up to 25% and 67%, respectively, compared to LPDDR, and reduce the execution time with up to 18% and 25%.
    01/2012; DOI:10.1109/DATE.2012.6176432
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    • "Additional dynamic random access memory can be stacked on top of the processor cores, significantly increasing the memory bandwidth [4]. The application of 3-D integration technology to microprocessors has received significant attention [5], [6]. Another important opportunity provided by 3-D technology is the ability to merge heterogeneous devices for a variety of applications including life sciences [7]. "
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    ABSTRACT: Three-dimensional (3-D) integration is a promising technology to alleviate the interconnect bottleneck by stacking multiple dies in a monolithic fashion. Both power dissipation and delay can be reduced by utilizing the third dimension where through silicon vias (TSVs) are used for vertical communication. Characteristics of switching noise that couples to a sensitive device due to a TSV are investigated in this paper. A model is developed to evaluate the noise performance of a TSV. Several noise isolation strategies are also discussed. Ignoring noise characteristics during the TSV placement process produces a poor 3-D circuit with high susceptibility to switching noise. I. INTRODUCTION Three dimensional (3-D) integration technology is a promis- ing candidate to maintain the benefits of miniaturization by utilizing the vertical dimension rather than decreasing the size of the devices in two dimensions (1)-(3). The advantages of 3-D integration technology include higher integration density and reduction in the length and number of the global intercon- nects. These advantages are utilized to reduce the existing gap between logic blocks and memory units in high performance microprocessors. Additional dynamic random access memory can be stacked on top of the processor cores, significantly increasing the memory bandwidth (4). The application of 3-D integration technology to microprocessors has received significant attention (5), (6).
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