Shape Engineering for Controlled Switching With Nanomagnet Logic
ABSTRACT We demonstrate that in circuits and systems that comprised of nanoscale magnets, magnet-shape-dependent switching properties can be used to perform Boolean logic. More specifically, by making magnets with slanted edges, we can shift the energy barrier of the device (i.e., so that it is not at a maximum when a device is magnetized along its geometrically hard axis). In clocked systems, we can leverage this barrier shift to make and or or gates that are not majority based. Advantages include reduced gate footprint and interconnect overhead as we eliminate one gate input. In this paper, we report and discuss micromagnetic simulations that illustrate how magnet shape can facilitate nonmajority-gate-based, reduced footprint logic; preliminary fabrication and testing results that illustrate that shape engineering can induce energy barrier shifts; and additional micromagnetic simulations that show other ways in which we might leverage shape in circuits made from nanoscale magnets.
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ABSTRACT: The recently proposed NanoMagnet based Logic (NML) represents an innovative way to assemble electronic logic circuits. The low power consumption, combined with the possibility to maintain the information stored without power supply, allows to design low power digital circuits far beyond the limitations of CMOS technology. This work is focused on the key logic block of NanoMagnet based Logic, the Majority Voter (MV). It is thoroughly analyzed through detailed micromagnetic simulations, changing the geometrical parameters, and detecting logic behavior, timing performance and energy dissipation. Our analysis enables to derive important results, substantially enhancing the practical knowledge of NML. First, we demonstrate that NML circuits can be effectively fabricated not only using Electron Beam Lithography, but also using high-end optical lithography without loosing performance. This is a promising opportunity for the future of this technology. Second, we demonstrate the robustness of the MV considering process variations and extracting useful guidelines for its technological implementation. Third, we show how, and how much, the alteration of magnets sizes and distances affect timing and energy consumption. Finally, fourth, we outline the problematic fabrication of the gate with real clock wires, and propose a modification that enables the fabrication of working gates, remarkably enhancing the possibilities of this technology.IEEE Transactions on Nanotechnology 01/2012; 11(5):940-947. · 1.80 Impact Factor
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ABSTRACT: The interest on emerging nanotechnologies has been recently focused on NanoMagnetic Logic (NML), which has unique appealing features. NML circuits have a very low power consumption and, due to their magnetic nature, they maintain the information safely stored even without power supply. The nature of these circuits is highly different from the CMOS one. As a consequence, to better understand NML logic, complex circuits and not only simple gates must be designed. This constraint calls for a new design and simulation methodology. It should efficiently encompass manifold properties: 1) being based on commonly used hardware description language (HDL) in order to easily manage complexity and hierarchy; 2) maintaining a clear link with physical characteristics 3) modeling performance aspects like speed and power, together with logic behavior. In this contribution we present a VHDL behavioral model for NML circuits, which allows to evaluate not only logic behavior but also power dissipation. It is based on a technological solution called “snake-clock”. We demonstrate this model on a case study which offers the right variety of internal substructures to test the method: a four bit microprocessor designed using asynchronous logic. The model enables a hierarchical bottom-up evaluation of the processor logic behavior, area and power dissipation, which we evaluated using as benchmark a division algorithm. Results highlight the flexibility and the efficiency of this model, and the remarkable improvements that it brings to the analysis of NML circuits.IEEE Transactions on Very Large Scale Integration (VLSI) Systems 08/2013; 1410-1420:21-8. · 1.22 Impact Factor
Conference Proceeding: Biosequences analysis on NanoMagnet Logic[show abstract] [hide abstract]
ABSTRACT: In the last decade Quantum dot Cellular Automata technology has been one of the most studied among the emerging technologies. The magnetic implementation, NanoMagnet Logic (NML), is particularly interesting as an alternative solutions to CMOS technology. The main advantages of NML circuits resides in the possibility to mix logic and memory in the same device, the expected low power consumption and the remarkable tolerance to heat and radiations. NML and QCA circuits behavior is different w.r.t. their CMOS counterparts. Consequently architecture organization must be tailored to their characteristics, and it is important to identify which applications are best suited for this technology. Our contribution reported in this paper represents a considerable step-forward in this direction. We present an optimized implementation on NML technology of an hardware accelerator for biosequences analysis. The architecture leverages the systolic array structure, which is the best organization for this technology due to the regularity of the layout. The circuit is described using a VHDL model, simulated to verify the correct functionality from the application point of view, and performance are evaluated, both in terms of speed and power consumption. Results pinpoints that NML technology with the appropriate clock solution can reach a considerable reduction in power consumption over CMOS. This analysis highlights quantitatively, and not only qualitatively, that NML logic is perfectly suited for Massively Parallel Data Analysis applicationsInternational Conference on IC Design and Technology; 01/2013