A 10-bit 100-MS/s Reference-Free SAR ADC in 90 nm CMOS

Abstract

A 1.2 V 10-bit 100 MS/s Successive Approximation (SA) ADC is presented. The scheme achieves high-speed and low-power operation thanks to the reference-free technique that avoids the static power dissipation of an on-chip reference generator. Moreover, the use of a common-mode based charge recovery switching method reduces the switching energy and improves the conversion linearity. A variable self-timed loop optimizes the reset time of the preamplifier to improve the conversion speed. Measurement results on a 90 nm CMOS prototype operated at 1.2 V supply show 3 mW total power consumption with a peak SNDR of 56.6 dB and a FOM of 77 fJ/conv-step.

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Y.??  Zhu,??  C.-­‐H.??  Chan,??  U.-­‐F.??  Chio,??  S.-­‐W.??  Sin,??  S.-­‐P??  U,??  R.P.??  Martins,??  F.??  Maloberti:??  “A??  10-­
bit??  100-­MS/s??  Reference-­Free??  SAR??  ADC??  in??  90??  nm??  CMOS”;??  IEEE??  Journal??  of??  Solid-­‐
State??  Circuits,??  Vol.??  45,??  No.??  6,??  June??  2010,??  pp.??  1111-­‐1121.??  
©20xx??  IEEE.??  Personal??  use??  of??  this??  material??  is??  permitted.??  However,??  permission??  to??  
reprint/republish??  this??  material??  for??  advertising??  or??  promotional??  purposes??  or??  for??  
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from??  the??  IEEE.??  

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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 45, NO. 6, JUNE 20101111
A 10-bit 100-MS/s Reference-Free SAR ADC
in 90 nm CMOS
Yan Zhu, Student Member, IEEE, Chi-Hang Chan, U-Fat Chio, Student Member, IEEE,
Sai-Weng Sin, Member, IEEE, Seng-Pan U, Senior Member, IEEE, Rui Paulo Martins, Fellow, IEEE, and
Franco Maloberti, Fellow, IEEE
Abstract—A 1.2 V 10-bit 100 MS/s Successive Approximation
(SA) ADC is presented. The scheme achieves high-speed and
low-power operation thanks to the reference-free technique that
avoids the static power dissipation of an on-chip reference gener-
ator. Moreover, the use of a common-mode based charge recovery
switching method reduces the switching energy and improves
the conversion linearity. A variable self-timed loop optimizes the
reset time of the preamplifier to improve the conversion speed.
Measurement results on a 90 nm CMOS prototype operated at
1.2 V supply show 3 mW total power consumption with a peak
SNDR of 56.6 dB and a FOM of 77 fJ/conv-step.
Index Terms—Charge-recovery, reference-free, switched tech-
nique.
I. INTRODUCTION
L
DVB-H and TDMB [1]. Since the ADCs operate at tens of
MS/s with 10 b to 12 b, the pipeline ADC is the commonly used
architecture because of its power efficiency [2]–[4]. However,
recently, the successive approximation register (SAR) architec-
ture has re-emerged as a valuable alternative to the pipelined
solution.
The conventional pipeline topology uses op-amps and
switched capacitor structures to generate the residual. More-
over, the internal flash uses
of bits of the stage). All these blocks burn up power. Moreover,
the reduction of supply voltage, as requested by sub-100 nm
technologies, increases the consumed power because the
reduced quantization step amplitude imposes an equivalent
OW POWER is the most relevant design concern for
battery-powered mobile applications, such as DVB-T,
comparators (n is the number
Manuscript received December 14, 2009; revised February 28, 2010; ac-
cepted March 24, 2010. Current version published June 09, 2010. This paper
was approved by Associate Editor Lucien Breems. This work was supported by
Research Grants from University of Macau and Macao Science and Technology
Development Fund (FDCT).
Y. Zhu, C.-H. Chan, U.-F. Chio, S.-W. Sin and S.-P. U are with Analog
and Mixed Signal VLSI Laboratory and Faculty of Science and Technology,
University of Macau, Macao, China (e-mail: yanjulia@ieee.org; http://www.
fst.umac.mo/en/lab/ans_vlsi/).
R. P. Martins is with Analog and Mixed Signal VLSI Laboratory and
Faculty of Science and Technology, University of Macau, Macao, China. He
is on leave from Instituto Superior Técnico/TU of Lisbon, Portugal (e-mail:
RMartins@umac.mo).
F. Maloberti is with the Electronic Department, University of Pavia, Italy,
and also with the University of Macau, Macao, China (e-mail: franco.mal-
oberti@unipv.it)
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/JSSC.2010.2048498
increase of the transconductance. Recent works [5]–[9] opti-
mize the power design of pipeline ADCs but the figure of merit
(FoM) remains in the hundred of fJ/conv-step range.
The pipeline architecture does not benefit from the tech-
nology scaling because the use of low voltage supplies gives
rise to an augmented consumption of power. In contrast, the
scaling of technology does not penalize much the SAR ADC
architecture because its analog part is simply made by a com-
parator and a capacitive DAC array. Indeed, the FoM values of
state-of-art SAR ADCs [10]–[12] are well lower than those of
pipelines and the best FoM in record is an SAR ADC [13]. The
FoM of a SAR converter that improves with thinner line-widths
is now in the range of tens of fJ/conv-step. However, for 65 and
90 nm technologies, the conversion rate is still low, not more
than 50 MS/s.
The speed of a SAR ADC is determined by the time required
by the DAC to settle within 1/2-LSB. With large number of bits
and capacitive arrays, the main cause of power consumption is
the reference generator that must provide very low output re-
sistance. A second important source of consumed power is the
dynamic power of the DAC. Previous works [12]–[14] improve
the conversion efficiency by saving part of the switching energy
during each bit cycling. However, the spared energy is a small
fraction of the total power dissipated by the reference voltage
generator, especially at high conversion speed [15]. Therefore,
the power efficiency improves if the power needed by the ref-
erence generator is not accounted for [9], [16], [17]. When this
power is included the FoM drops significantly.
This design obtains remarkable power effectiveness for
medium resolution and high conversion speed by using two
strategies: the first avoids the reference generator by directly
using the supply voltages; the second saves the switching
energy during the SA conversion. The use of the supply voltage
as the reference of the ADC would lead to a signal swing of
the converter that is wider than the typical signal range; this
would reduce the effective SNR. This drawback is removed
with the proposed technique that grants a passive gain by 2
of the input. A doubling of the LSB, that relaxes the limits of
noise and offset, also lowers the power consumption of the
comparator. In addition, it is worth to notice that a multiplica-
tion by 2 enables an input signal that is half the rail-to-rail and
not the full rail-to-rail as is presented in [12], [13], [18], [19].
Having an input range of the converter well within the supply
limit is suitable for signals generated on-chip. This is very
common because the input of an ADC is the result of on-chip
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1112IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 45, NO. 6, JUNE 2010
Fig. 1. Overall schematic diagram of the ADC architecture.
pre-conditioning, like amplification or filtering, obtained with
op-amps whose signal swing represents headroom from the
supply limits.
The switching energy saving technique, described in detail
below, avoids the mismatch error at the conventional most sig-
nificant bit (MSB) transition and enables a reduction by 2 of
the overall capacitance used in the SAR. The charge recovery,
implemented during each bit cycling, cuts by 1/3 the switching
energy with respect to the one achieved in [12]. In addition, the
used switching approach improves the conversion linearity that
typically affects a conventional SAR ADC.
Instead of using the asynchronous processing [16] this paper
avoidsthefast clockbyimplementinga variableself-timedloop
that adjuststheplus width ofthepreamplifier to reduce theideal
time for the LSBs conversions.
II. ADC ARCHITECTURE
Fig. 1 shows the architecture of the proposed 10-bit SAR
ADC. It comprises differential capacitor networks, a dynamic
comparator and the SA control logic. The differential capacitor
networks are composed by 10-bit split schemes with the addi-
tional sampling capacitors
necessary for the passive multi-
plication by 2. The SA logic controls
for bringing it toward
comparator, the 4 inputs preamplifier and the dynamic latch
determine the value of each bit. The SA control logic includes
shift registers, bit registers and a switching logic block, which
control the DAC operation to perform the binary-scaled feed-
back during the successive approximation cycle. The frequency
of the clock used by the SA block is the ADC sampling fre-
quency. No fast clock at the input is needed because the SA
uses the self-timed technique. All the SA control signals re-
sult from a proper use of internal delay lines and their logic
combination.
As mentioned in the introduction, the scheme presented in
the next sub-section obtains as a great benefit the equivalent
multiplication by two of the input. This permits the reference
free operation and enhances the profit of charge recovery, thus
reducing power consumption.
. In the
Fig. 2. Conceptual scheme that obtains a passive gain by 2.
A. Passive Multiplication by 2
A well-known feature of many SAR architectures is their
insensitivity to parasitic capacitances. With conventional ap-
proaches the input of the comparator is at the reference voltage
in the beginning of the conversion cycle and draws near the ref-
erenceat theend of theconversion.As a result, the chargeof the
parasiticcapacitanceisalmostthesameatthebeginningandthe
end of the conversion cycle. The schemes that are sensitive to
parasiticexperienceagainerrorandalinearityerror.Obviously,
the gain error due to the top-plate parasitic of DAC is not very
important as it corresponds to an error of the voltage reference.
More relevant is the non-linearity of the preamplifier input par-
asitic: the variation of the gate voltage may degrade the integral
nonlinearity(INL). However,thisparasiticnonlinearity effectis
irrelevant: the parasitic of the preamplifier input is quite small
when compared with the total capacitance of the DAC array.
Therefore, the SAR ADC is, in practice, insensitive to the par-
asitic effects of both the DAC array and preamplifier. Conse-
quently, for medium resolutions, parasitic insensitivity can be
traded with other more valuable features. This design trades the
parasitic insensitivity with the passive amplification by 2.
The conceptual scheme of Fig. 2 illustrates the method.
During the sampling phase the binary-weighted capacitive
DAC samples the input, like in a conventional scheme, while
samples the complementary input. During the conversion
phase
shifts the voltage of the reference node to
making equal to
the signal that the SAR algorithm must
compensate for.
The conventional SAR algorithm drives the DAC to finally
converge to the common mode voltage
bit-cycling, according to
,
at the end of the
(1)
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ZHU et al.: A 10-bit 100-MS/s REFERENCE-FREE SAR ADC IN 90 nm CMOS1113
Fig. 3. The ???-based switching timing diagram with its n-bit split capacitive DAC array ?? ? ? ? ??.
on the contrary, the proposed method drives the DAC to con-
verge toward
instead of
(2)
(3)
In the above equations
bit n and
the reference voltage
Moreover, (3) certifies that the proposed operation corresponds
to a passive amplification by 2 of the input. Furthermore, the
proposed technique uses a reference voltage,
twice
, as used in the conventional counterpart. This is a
key feature for the use of the supply voltage as reference. With
identicaltothesupplyvoltage,thesignalswing
is 0.3–0.9 V with
, a value that allows the ADC to
use signals generated by on-system stages biased by the supply
voltage.
The sampling capacitor
serves to hold the input signal for
theSAconversion,consequentlynospecificmatchingcondition
is required between
and the DAC array. However,
be large enough to comply with the
In addition to the supply voltages this architecture uses the
common mode voltage to pre-charge the capacitors. However,
since the processing is fully-differential, no charge flows
through the common mode terminal, unless there is a mismatch
between the used common modeand theone of theinput signal.
Assuming that the mismatch is less than 10%, the common
mode generator must provide a limited charge: 10 times smaller
than what is required to references used in conventional SAR
converters. Therefore, the output resistance of the common
mode generator and its power needs are significantly relaxed.
(1 or 0) is the ADC decision for
represents the capacitors connected to
and the total array capacitance.
,
, that is
must
noise constraint.
B.
-Based Switching Method
Switching the capacitive array consumes significant power.
In order to reduce this term the value of the unit capacitance
must be brought down to the limit allowed by the technology
and the
noise. Moreover, the use of the split capacitive
array, that substitutes the full binary-weighted array, helps in
thepowerreductionbecausethemethodreducesthetotalcapac-
itance of the arrays. Further energy saving is obtained with ef-
fectiveswitchingapproaches[12]–[14],[20],[21].Oneofthem,
the set-and-down method recently proposed [12], saves signif-
icant switching energy thanks to its halving of the overall ca-
pacitance. The method used here, named
approach,also obtains a half-capacitancereduction. Inaddition,
as shown below, the switching sequence reduces the energy by
an additional 1/3 with respect to the set-and-down technique.
The
-based switching approach determines the sign of
the differential input (MSB) by connecting the differential ar-
rays to
. The power dissipation is just derived from what is
needed to drive the bottom-plate parasitic of the capacitive ar-
rays, while in the conventional charge-redistribution [13], [22]
and the charge-recycling [14] methods the necessary MSB “up”
transition costs significant switching energy and settling time.
Moreover, the MSB capacitor, being not required anymore, can
be removed from the n-bit DAC array. Therefore, the next
estimation is done with an
n-bit counterpart, leading to half capacitance with respect to the
conventional and charge-recycling methods.
Fig. 3 details the
-based switching algorithm. In the
global sampling phase
,
During the resting phase
, all the capacitors’ bottom-plates
are switched to the common-mode voltage, resulting in the
equivalent output voltage
determines the MSB during
controls
. If,
other switches
remain connected to
result is that the voltage at
-based switching
bit array instead of its
is stored in the capacitor array.
at the output. The value of
as the logic properly
goes towhile the
. The
[2] becomes.
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1114IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 45, NO. 6, JUNE 2010
Fig. 4. A 3-bit example of set-and-down and proposed ???-based switching procedures.
If, is switched to
. The cycle is repeated for
, raising the voltage at
[2] to
TheschemeofFig.3andtheabovedescriptionareforasingle
endedoperation.Inreality,thefullydifferentialoperationmakes
the algorithm insensitive to the input common mode,
The difference between the common mode input and
mines equal shifts
Fig.3.Theseshifts,assumedwithinthelimitsofthecomparator
common mode range, are rejected being a common mode com-
ponent. Moreover, the
-based switching method foresees
“up” or “down” transitions after the comparator determines the
bit and not before. This does not require pre-charging of capaci-
torsand,possibly,theirdischargingafterthebitdecision.There-
fore,theperformedcharge-redistributionisjustwhatisrequired
without wasting power. The only additional cost of this method
is that it uses n more switches to initially reset all the capacitors
to a common-mode voltage.
times.
.
deter-
of the output of the array of
C. Charge-Recovery
The
-based switching method operates in a similar way
as the set-and-down [12] technique. Both reduce the capaci-
tive array and simplify the MSB transition. However, for the
determinations of the remaining
switching sequence.
To outline the difference between the two methods Fig. 4
shows the operational steps of a 3-bit differential capacitive
array performing the -based charge recovery and the
there is a different
set-and-down methods. From [12] when the supply is directly
used as the reference voltage, a rail-to-rail input signal is
required. Fig. 4 illustrates the case where the input signal of the
two methods is in both rail-to-rail. Accordingly, the reference
voltage
and the common-mode voltage
approaches are equal to
and
switching energy needed for the first bit comparison is just what
is necessary for driving the bottom-plate parasitics of the DAC
arrays. Since the
-based method charges the parasitic to
half of the reference voltage, while the set-and-down uses the
full reference, the consumed energy for the first bit comparison
of the
-based method is half of the set-and-down. The
parasitic capacitance depends on technology and layout. Its
value can be large because for medium and high-resolutions
it is necessary to use electronic shielding on the top and the
bottom which prevents couplings and noise injections.
The value of the MSB sets the arrays for second bit estima-
tion. The SA logic controls the 2C of the
for “up” or “down” transition, respectively, as indicated also
in Fig. 4, and the DACs’ outputs finally settle to the following
values:
in the two
, respectively. The
and
(4)
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