A Low-Power Ultrawideband CMOS Power Detector With an Embedded Amplifier
ABSTRACT A self-biased low-power CMOS power detector (PD) is proposed and demonstrated in this paper. The detector utilizes the nonlinear characteristics of short-channel MOS devices operating in either a saturation or subthreshold regime to generate a dc current that is proportional to the input RF signal power. The operating regimes of MOS devices depend on input RF power levels. A quasi-T-coil matching network providing 50- matching from 0.5 to 20 GHz is designed and analyzed. An embedded amplifier is added to enhance the sensitivity of the PD when the input power level is low. The circuit that is implemented in a 0.13- CMOS process occupies an active area of 0.085 . In the matched frequency range, the measured input dynamic range is 47 dB with an overall sensitivity of 26.8 mV/dB. The output dc voltage response is nearly frequency-independent in the linear operating range, varying by less than 1.9 dB for a given input RF power level, as the RF frequency is swept across the operating frequency range. With a standard 1.2-V supply, the static power consumption is about 0.1 mW, which decreases to with a 0.5-V supply, while the operating frequency remains unchanged.
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ABSTRACT: Multi(six)-port impulse radio (MIR) validates the full channel (3-4 GHz) novel quaternary phase spectrum modulation (QPSM) scheme using a six-port modulator and demodulator circuits. Due to the lack of a monocycle generator, a 1-GHz spectral phase channel is generated from a rectangular pulse signal, upconverted using filters, mixer, and a local oscillator. The 3-4-GHz signal is applied to the RF input of a six-port modulator and digital data is simultaneously fed to a switch matrix terminating four ports of the modulator with either a short or open circuit. This operation produces an output signal in the QPSM scheme. One input port of the six-port demodulator is fed with the received phase-modulated signal and a second input port is fed with the reference nonmodulated signal. The demodulator's four outputs provide signals of different amplitudes used to determine the modulation states with digital signal processing (DSP) algorithms. Modulation algorithms, demodulation algorithms, and synchronization control are implemented on a field-programmable gate-array-based DSP platform fitted with four analog-to-digital converters. Measurements and simulation results are presented to validate the MIR hardware and software in an operating 1-GHz ultra-wideband channel.IEEE Transactions on Microwave Theory and Techniques 07/2006; · 2.23 Impact Factor
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ABSTRACT: This paper introduces a low-power ultra-wideband true root-mean-square power detector with a 0.13-mum CMOS process operating from 125 MHz to 8.5 GHz. The detector utilizes the MOS transistor's square-law characteristic in the strong inversion region to obtain the power information of the input RF signal, and its exponential characteristic in the weak inversion region to realize the linear-in-decibel output. Measured dynamic ranges are 20 dB at 125 MHz and 18 dB at 8.5 GHz, respectively, with tolerances of plusmn0.5-dB error. WiMedia-ultrawideband and wireless local area network 802.11a signals with different modulation techniques and data rates are measured. The integrated detector operates at 1.2-V supply voltage, and its static power consumption is 0.18 mW.IEEE Transactions on Microwave Theory and Techniques 06/2008; · 2.23 Impact Factor
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ABSTRACT: This paper describes a CMOS programmable gain amplifier (PGA) that maintains a 3-dB bandwidth greater than 110 MHz and can provide an 84-dB gain control range with 1-dB step resolution. The PGA can also be operated in a low-power mode with 3-dB bandwidth greater than 71 MHz. Integrated with this PGA is a CMOS successive logarithmic detecting amplifier with a ±0.7-dB logarithmic accuracy over an 80-dB dynamic range. It achieves -83-dBm sensitivity and consumes 13 mA from a single 3-V supply in the normal power mode. The chip area, including pads, occupies 1.5×1.5 mm<sup>2</sup>.IEEE Journal of Solid-State Circuits 07/2005; · 3.06 Impact Factor