A 64Mb MRAM with clamped-reference and adequate-reference schemes
ABSTRACT A 64 Mb spin-transfer-torque MRAM in 65 nm CMOS is developed. A 47 mm2 die uses a 0.3584 Â¿m2 cell with a perpendicular-TMR device. To achieve read-disturb immunity for the reference cell, a clamped-reference scheme is adopted. An adequate-reference scheme is implemented to suppress read-margin degradation due to the resistance variation of reference cells.
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ABSTRACT: An important task of micro-and nanoelectronics is establishing a new universal memory type in a near future. Unlike DRAM and flash memories a new universal memory should not require electric charge storing, but alternative principles of information storage. For successful application a new universal memory has to be non-volatile and must also exhibit low operating voltages, low power consumption, high operation speed, long retention time, high endurance, and a simple structure. Several alternative principles of information storage are available. We focus on two memory technologies based on the resistance change principle, RRAM and the spin transfer torque (STT) RAM, which are the most promising candidates for future universal memory. We present a brief overview of the current state-of-the-art of these technologies and outline future trends and challenges from the perspective of modeling and simulation of the switching process.Physics Procedia 01/2012; 25.
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ABSTRACT: Emerging non-volatile memories (NVM) such as STT-MRAM and OxRRAM are under intense investigation by both academia and industries. They are based on resistive switching mechanisms and promise advantageous performances in terms of access speed, power consumption and endurance (i.e. >1012), surpassing mainstream flash memories. This paper presents a non-volatile full-adder design based on complementary resistive switching memory cells and validates it through two NVM technologies: STT-MRAM and OxRRAM on 40 nm node. This architecture allows low power consumption. Thanks to the nonvolatility and 3D integration of NVM, both standby power during “idle” state and data transfer power can be reduced. Using a low changing frequency can also control the switching power of NVM. The complementary cells and parallel data sensing enable fast computation and high reliability.2013 IEEE 11th International New Circuits and Systems Conference (NEWCAS), Paris, France; 06/2013
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ABSTRACT: This paper describes a proposal of non-volatile cache architecture utilizing novel DRAM / MRAM cell-level hybrid structured memory (D-MRAM) that enables effective power reduction for high performance mobile SoCs without area overhead. Here, the key point to reduce active power is intermittent refresh process for the DRAM-mode. D-MRAM has advantage to reduce static power consumptions compared to the conventional SRAM, because there are no static leakage paths in the D-MRAM cell and it is not needed to supply voltage to its cells when used as the MRAM-mode. Besides, with advanced perpendicular magnetic tunnel junctions (p-MTJ), which decreases the write energy and latency without shortening its retention time, D-MRAM is capable of power reduction by replacing the traditional SRAM caches. Considering the 65-nm CMOS technology, the access latencies of 1MB memory macro are 2.2 ns / 1.5 ns for read / write in DRAM mode, and 2.2 ns / 4.5 ns in MRAM mode, while those of SRAM are 1.17 ns. The SPEC CPU2006 benchmarks have revealed that the energy per instruction (EPI) of the total cache memory can be dramatically reduced by 71 % on average, and the instruction per cycle (IPC) performance of the D-MRAM cache architecture degraded only by approximately 4 % on average in spite of its latency overhead.Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013; 01/2013