A 64Mb MRAM with clamped-reference and adequate-reference schemes
ABSTRACT A 64 Mb spin-transfer-torque MRAM in 65 nm CMOS is developed. A 47 mm2 die uses a 0.3584 Â¿m2 cell with a perpendicular-TMR device. To achieve read-disturb immunity for the reference cell, a clamped-reference scheme is adopted. An adequate-reference scheme is implemented to suppress read-margin degradation due to the resistance variation of reference cells.
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ABSTRACT: As one recently introduced non-volatile memory (NVM) device, domain-wall nanowire (or race-track) has shown potential for main memory storage but also computing capability. In this paper, the domain-wall nanowire is studied for a memory-based computing platform towards ultra-low-power big-data processing. One domain-wall nanowire based logic-in-memory architecture is proposed for big-data processing, where the domain-wall nanowire memory is deployed as main memory for data storage as well as XOR-logic for comparison and addition operations. The domain-wall nanowire based logic-in-memory circuits are evaluated by SPICE-level verifications. Further evaluated by applications of general-purpose SPEC2006 benchmark and also web-searching oriented Phoenix benchmark, the proposed computing platform can exhibit a significant power saving on both main memory and ALU under the similar performance when compared to CMOS based designs.ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED); 09/2013
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ABSTRACT: In this paper we analyze the possibility of creating a universal non-volatile memory in a near future. Unlike DRAM and flash memories a new universal memory should not require electric charge storing, but alternative principles of information storage. For the successful application a new universal memory must also exhibit low operating voltages, low power consumption, high operation speed, long retention time, high endurance, and a simple structure. Several alternative principles of information storage are reviewed. We discuss different memory technologies based on these principles, highlight the most promising candidates for future universal memory, make an overview of the current state-of-the-art of these technologies, and outline future trends and possible challenges by modeling the switching process.Microelectronics Reliability 08/2013; DOI:10.1016/j.microrel.2011.10.020 · 1.21 Impact Factor
- ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED); 08/2012