Conference Paper

A 64Mb MRAM with clamped-reference and adequate-reference schemes

Toshiba, Yokohama, Japan
DOI: 10.1109/ISSCC.2010.5433948 Conference: Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International
Source: IEEE Xplore


In order to realize a sub-Giga bit scale NVRAM, the novel MRAM based on the spin-transfer-torque (STT) switching has been intensively investigated due to its excellent scalability compared with a conventional magnetic field induce switching MRAM [1]. However, the memory cell size of STT-MRAM reported so far is still over 1μm2, and the memory capacity is limited to 32Mbit even in almost 100mm2 die size [2]. The large cell size is due to the large switching current of MRAM cells. In order to reduce the cell size, we have proposed the perpendicular tunnel magnetoresistance (P-TMR) device, and have confirmed its high potential to achieve lower switching current [3]. In this paper, a 64Mb STT-MRAM with the P-TMR device having the circuit techniques to maximize operational margin is described.

25 Reads
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    • "The distance from BLMUX to SLMUX of the data cell is shorter than that of the reference cell, and thus, parasitic and resistance mismatch occurs between the data and reference cells. To overcome the mismatch problem, the same parasitic scheme was proposed in [4]. By placing the SLMUX at the opposite side of the BLMUX, the distances from the BLMUX to SLMUX of the data and reference cells become identical, as shown in Fig. 5 "
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    ABSTRACT: As technology scales down, the sensing margin of spin-transfer-torque random access memory is significantly degraded because of the increased process variation and decreased supply voltage. The sensing current, which is limited to prevent read disturbance, further degrades the sensing margin. To improve the sensing margin, various reference schemes have been proposed. However, it is essential to be selective because the read stability, write ability, and array efficiency are very different according to the reference schemes. This paper presents the study of a variety of reference schemes and outlines five requirements for an optimized reference scheme as follows: 1) no parasitic mismatch, 2) no regularity problem, 3) no read disturbance, 4) no write-current degradation, and 5) small area overhead. A novel reference scheme that satisfies all the requirements for the optimized reference scheme is proposed using four 1T1MTJ cells and a reference word line structure with the same parasitic scheme.
    Circuits and Systems I: Regular Papers, IEEE Transactions on 12/2014; 61(12):3376-3385. DOI:10.1109/TCSI.2014.2327337 · 2.40 Impact Factor
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    • "As such, a power-efficient memory-based design is highly desirable for future big-data processing. Towards this end, there are many recent explorations by the newly discovered non-volatile memory (NVM) technologies such as phase-change memory (PCM), spin-transfer torque memory (STT-RAM), and resistive memory (ReRAM) [2], [3], [4], [5], [6], [7], [8]. The primary advantage of NVM is the potential as the universal memory with significantly reduced leakage power. "
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    ABSTRACT: As one recently introduced non-volatile memory (NVM) device, domain-wall nanowire (or race-track) has shown potential for main memory storage but also computing capability. In this paper, the domain-wall nanowire is studied for a memory-based computing platform towards ultra-low-power big-data processing. One domain-wall nanowire based logic-in-memory architecture is proposed for big-data processing, where the domain-wall nanowire memory is deployed as main memory for data storage as well as XOR-logic for comparison and addition operations. The domain-wall nanowire based logic-in-memory circuits are evaluated by SPICE-level verifications. Further evaluated by applications of general-purpose SPEC2006 benchmark and also web-searching oriented Phoenix benchmark, the proposed computing platform can exhibit a significant power saving on both main memory and ALU under the similar performance when compared to CMOS based designs.
    ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED); 09/2013
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    • "From these technologies two of the most promising candidates for future universal memory are STTRAM and Redox Resistive RAM. Currently, STTRAM, RRAM and CBRAM have been demonstrated on 64 Mb [3], 4 Mb [4] [5] test chips, respectively. These technologies would be manufacturable within 5–10 years [6]. "
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    ABSTRACT: In this paper we analyze the possibility of creating a universal non-volatile memory in a near future. Unlike DRAM and flash memories a new universal memory should not require electric charge storing, but alternative principles of information storage. For the successful application a new universal memory must also exhibit low operating voltages, low power consumption, high operation speed, long retention time, high endurance, and a simple structure. Several alternative principles of information storage are reviewed. We discuss different memory technologies based on these principles, highlight the most promising candidates for future universal memory, make an overview of the current state-of-the-art of these technologies, and outline future trends and possible challenges by modeling the switching process.
    Microelectronics Reliability 08/2013; DOI:10.1016/j.microrel.2011.10.020 · 1.43 Impact Factor
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