Conference Proceeding

A 86MHz-to-12GHz digital-intensive phase-modulated fractional-N PLL using a 15pJ/Shot 5ps TDC in 40nm digital CMOS

IMEC, Leuven, Belgium
Digest of Technical Papers - IEEE International Solid-State Circuits Conference 03/2010; DOI:10.1109/ISSCC.2010.5433840 pp.480 - 481 In proceeding of: Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International
Source: IEEE Xplore

ABSTRACT A 86 MHz-12 GHz digital-intensive reconfigurable synthesizer is presented with 100 kHz to 2 MHz bandwidth. It leverages a 15 pJ/Shot 5.5 ps 14 b coarse-fine TDC and a 6-to-12 GHz dual-VCO set. The 0.28 mm2 synthesizer features simple background calibration, ¿¿ noise cancelation, and digital phase modulation, and consumes less than 30 mW.

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Keywords

0.28 mm<sup>2</sup> synthesizer features simple background calibration
 
2 MHz bandwidth
 
6-to-12 GHz dual-VCO
 
¿¿ noise cancelation
 

Vito Giannini