A 86MHz-to-12GHz digital-intensive phase-modulated fractional-N PLL using a 15pJ/Shot 5ps TDC in 40nm digital CMOS
ABSTRACT A 86 MHz-12 GHz digital-intensive reconfigurable synthesizer is presented with 100 kHz to 2 MHz bandwidth. It leverages a 15 pJ/Shot 5.5 ps 14 b coarse-fine TDC and a 6-to-12 GHz dual-VCO set. The 0.28 mm2 synthesizer features simple background calibration, Â¿Â¿ noise cancelation, and digital phase modulation, and consumes less than 30 mW.
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ABSTRACT: This paper presents an all-digital PLL (ADPLL) in which all functional blocks have been synthesized from standard digital cells and automatically placed and routed (P&R). A calibration scheme is proposed to account for the systematic mismatch resulting from P&R. The ADPLL is fabricated in 65nm CMOS and occupies 0.042mm2. The period jitter is 3.2psrms (36pspp) at 2.5GHz, and the power consumption is 9.1mW to 14.6mW over a 1.5 to 2.7GHz frequency range.2011 IEEE Custom Integrated Circuits Conference, CICC 2011, San Jose, CA, USA, Sept. 19-21, 2011; 01/2011
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ABSTRACT: A compact (0.01mm<sup>2</sup>) coarse-fine time-to-digital converter (TDC) in 40nm LP CMOS achieves 5.5ps resolution using parallel delay lines. A 6fJ/conversion step efficiency is achieved thanks to efficient residue calculation. A 0.8LSB single-shot precision and low DNL are reached thanks to simple calibration which is possible in fractional-N PLLs. Further, metastability avoidance and digital error correction are implemented. This 14-bit architecture operates at a 40MS/s reference clock.Radio Frequency Integrated Circuits Symposium (RFIC), 2010 IEEE; 06/2010
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ABSTRACT: A 2GHz, ring-oscillator based Digital PLL (DPLL) with temperature lock range of -40°C to 125°C is presented here. The Digitally Controlled Oscillator (DCO) of the DPLL consists of a current mode Digital to Analog Converter (DAC) followed by a Current Controlled Oscillator (ICO). The current mode DAC is designed such that the outputs of any two adjacent current elements can be progressively brought out for separate ΣΔ operation. This increases the DAC range and hence the DPLL temperature lock range, even as the ΣΔ step size and range are kept small to minimize jitter. The DPLL achieves a phase noise of -90dBC/Hz at 1MHz offset for 2GHz operation. It supports an input frequency range of 0.5MHz to 50MHz, occupies a core area of 0.09mm 2 and consumes 7.2mW. In (7), a double integral path and an additional Compensation ΣΔ DAC are used to extend the range of the DCO. This work presents a DPLL that uses a new, scalable architecture for ring-oscillator based DCOs. The DCO consists of a current mode DAC followed by a Current Controlled Oscillator (ICO). The current mode DAC is designed such that outputs of any two adjacent current elements can be progressively brought out of the main DAC for separate ΣΔ operation. The ΣΔ operating range of the DCO at any point is thus equivalent to two DAC steps, while the overall DCO range is equivalent to the total number of DAC elements. This enables the DCO to track temperature over a large range, even as the ΣΔ step size and range are kept small to minimize jitter. The proposed architecture obviates the need for separate corrections to track temperature, as used in (4)(5)(8) or for a double integral path to extend DCO range, as used in (7). The rest of the paper is organized as follows. Section II first briefly discusses the top-level DPLL architecture, and then explains the proposed DCO architecture in detail. Details from a 45nm implementation are described. Silicon results are presented and compared with the state of the art in Section III. Conclusions are presented in section IV.2011 IEEE Custom Integrated Circuits Conference, CICC 2011, San Jose, CA, USA, Sept. 19-21, 2011; 01/2011