Optimization of metallization processes for 32-nm-node highly reliable ultralow-k (k=2.4)/Cu multilevel interconnects incorporating a bilayer low-k barrier cap (k=3.9)
ABSTRACT Reliability of 32-nm-node ultralow-k (k=2.4)/Cu multilevel interconnects incorporating a bilayer low-k barrier cap (k=3.9) was improved without excessive wiring resistance by using CuAl seed technology with high-temperature and short-time annealing. Though the increase in wiring resistivity was about 10%, both electromigration (EM) and stress-induced voiding (SiV) reliability was clearly improved by using Cu-0.5 wt%Al seed metal.
Conference Proceeding: Thermal stress of 140 nm-width Cu damascene interconnects[show abstract] [hide abstract]
ABSTRACT: We found two failure modes induced by thermal process at 150°C and 350°C in 140 nm Cu interconnects. One is two-dimensional (2D) agglomeration in which 140 nm-width line metal is pulled into the wider root metal. The other is three-dimensional (3D) agglomeration in which 130 nm via metal is pulled toward the upper wide metal. 140 nm Cu structural analysis using EXAFS also shows two types of structure change, presumably corresponding to each failure modes.Interconnect Technology Conference, 2002. Proceedings of the IEEE 2002 International; 02/2002
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ABSTRACT: We used an optical beam induced resistance changes (OBIRCH) method to analyze defects in 0.10-μm-wide Cu lines. Narrower lines and higher annealing temperatures strongly increased the defects probably due to Cu film agglomeration in very narrow line trenches. SiC capping of Cu lines reduced the numbers of defects drastically. Capping material is a key factor for 0.10-μm-wide, Cu metallizationInterconnect Technology Conference, 2001. Proceedings of the IEEE 2001 International; 02/2001
Conference Proceeding: Impact of Cu microstructure on electromigration reliability[show abstract] [hide abstract]
ABSTRACT: The effect of Cu microstructure on electromigration (EM) has been investigated. A variation in the Cu grain size distributions between wafers was achieved by adjusting the wafer annealing process step after Cu electroplating and before Cu chemical mechanical polishing. Void growth morphology was observed by in-situ and ex-situ scanning electron microscope (SEM) techniques. The Cu lifetime and mass flow in samples with bamboo, near bamboo, bamboo-polycrystalline mixture, and polycrystalline grain structures were measured. The introduction of polycrystalline Cu line grain structure in fine lines for the 65 nm node technology and beyond markedly reduced the Cu EM reliability. The smaller Cu grain size distribution resulted in a shorter EM lifetime and a faster mass flow. The EM activation energies for Cu along Cu/amorphous a-SiC<sub>x</sub>N<sub>y</sub>H<sub>z</sub> interface and grain boundary were found to be 0.95 and 0.79 eV, respectively.International Interconnect Technology Conference, IEEE 2007; 07/2007