RF power potential of 45 nm CMOS technology

Abstract

This paper presents the first measurements of the RF power performance of 45 nm CMOS devices with varying device widths and layouts. We find that 45 nm CMOS can deliver a peak output power density of around 140 mW/mm with a peak power-added efficiency (PAE) of 70% at 1.1 V. The PAE and P_out decrease with increasing device width because of a decrease in the maximum oscillation frequency (f_max) for large width devices. The PAE also decreases with increasing frequency because of a decrease in gain as the operating frequency approaches f_max. The RF power performance of 45 nm devices is shown to be very similar to that of 65 nm devices.

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RF Power Potential of 45 nm CMOS Technology
Usha Gogineni
1, Jesús A. del Alamo
1, and Christopher Putnam
2
1Massachusetts Institute of Technology, Cambridge, MA,
2IBM Microelectronics, Essex Jct, VT


Abstract − This paper presents the first measurements of
the RF power performance of 45 nm CMOS devices with
varying device widths and layouts. We find that 45 nm CMOS
can deliver a peak output power density of around 140
mW/mm with a peak power-added efficiency (PAE) of 70% at
1.1 V. The PAE and Pout decrease with increasing device width
because of a decrease in the maximum oscillation frequency
(fmax) for large width devices. The PAE also decreases with
increasing frequency because of a decrease in gain as the
operating frequency approaches fmax. The RF power
performance of 45 nm devices is shown to be very similar to
that of 65 nm devices.
I. INTRODUCTION
The remarkable improvement in the frequency response
of silicon CMOS devices in recent years has motivated
their use in millimeter-wave power applications. Specific
applications in the millimeter-wave regime include high
capacity wireless LAN, short-range high data-rate wireless
personal area networks, and collision avoidance radar for
automobiles. Using silicon CMOS for these applications
allows for higher levels of integration and lower cost. Also,
special circuits for improving efficiency and linearity of
power amplifiers can be easily integrated into CMOS.
The state-of-the-art technology for 60 GHz power
amplifier designs today is the 65 nm technology [1-2].
Recently a few research groups have demonstrated 60 GHz
power amplifiers in 45 nm technologies [3-4]. However, a
detailed study of the power performance of 45 nm
technology has not been published so far.
In this paper, we present a comprehensive study of the
RF power performance of 45 nm low-power CMOS
devices. Device structures with different layouts and widths
are studied to understand the effect of device geometry on
RF power performance. A comparison of the RF power
capability of 45 nm and 65 nm technologies is also
presented. We show that PAE and Pout decrease with
increasing device width because of a reduction in fmax. The
RF power performance of 45 nm devices is shown to be
very similar to that of 65 nm devices.
II. TECHNOLOGY
The devices used in this study are 45 nm low-power
CMOS [5, 6] and 65 nm CMOS [7] devices from IBM. The
45 nm devices all have a gate length of 40 nm and VDD =
1.1 V, while the 65 nm devices have a gate length of 50 nm
and VDD = 1 V. For the 45 nm devices, the device width is
increased by either (a) keeping the number of fingers (NF)
constant (NF=60) and increasing the unit finger width
(WF) from 0.5 μm to 5 μm, or (b) keeping the finger width
constant (WF=1.5 μm) and increasing NF from 20 to 120.
For the 65 nm devices, the device width is increased by
connecting multiple unit cells in parallel. Each unit cell has
12 fingers of 2 μm finger width.
S-parameter measurements from 0.5 GHz to 40 GHz
were performed using an Agilent 8510C. The S-parameter
data was de-embedded using on-wafer open and short de-
embedding structures that were custom designed for each
device. RF power measurements were made in the 2 GHz –
18 GHz range using a Maury Microwave load-pull system.
Unless otherwise indicated, all S-parameter and power
measurements were done at VDS = VDD and VGS set to
ensure an identical DC drain current density across devices
under low input power conditions..
III. 45 NM MEASUREMENTS
S-parameter and RF power measurements were made
on 45 nm device structures with different geometries in an
effort to understand the effect of device layout and width
on RF power performance.
The first set of test structures explores the effect of
contacting the gate at one end or at both ends of the gate
finger. Fig. 1 compares the de-embedded fT and fmax of a
single gate contact structure with that of a double gate
contact structure as a function of bias current. A double
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fT(GHz)
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Fig. 1: fT and fmax as a function of drain current density for single
and double gate contact structures.
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gate contact results in a significantly lower gate resistance,
but a slightly higher gate capacitance. This leads to a
slightly lower fT for the double gate contact structure
compared to single gate contact at the same drain current
density. However, fmax is higher in the double gate contact
structure because the reduction in gate resistance more than
compensates for the increase in gate capacitance. The
improvement in fmax is more pronounced at higher current
densities.
Fig. 2 shows the PAE and normalized output power
(Pout/W), measured at ID = 200 mA/mm and VDD = 1.1 V,
as a function of measurement frequency for the single and
double gate contact structures. The load and source
impedances were tuned for optimum PAE and the output
power and PAE were measured at peak PAE. The PAE for
the double gate contact is similar to that of the single gate
contact structure. The PAE is also remarkably frequency
independent. The output power is slightly higher for the
double gate contact structure.
Fig. 3 shows the impact of number of fingers (NF) and
finger width (WF) on de-embedded fmax. The devices with
the same WF are connected by solid lines. The numbers
beside each symbol denote the number of fingers in that
device. All devices used in this study and in the rest of the
paper have double gate contacts. It is clear from Fig. 3 that
fmax decreases with increasing total device width. For a
given NF, increasing WF initially leads to an increase in
fmax but eventually fmax decreases as the gate resistance
increases. The optimum unit finger width for this
technology is 1.5 μm. On the other hand, for a given WF,
increasing NF leads to a decrease in fmax. This is because of
the increased parasitic resistance resulting from the
additional wiring needed to connect all the fingers in
parallel.
The peak PAE for the NF=60 structures is shown as a
function of total device width for different measurement
frequencies in Fig. 4. PAE increases with width for small
device widths (W < 100 μm) because of an increase in
power gain as a result of lower relative parasitics. For W >
100 μm, PAE is constant with width at lower frequencies
but tends to decrease with width at higher frequencies
because of the reduction in gain with frequency.

Fig. 4: PAE, measured at different frequencies, as a function of
total device width. Device width is increased by keeping NF
constant at 60 and increasing WF from 0.5 μm to 5 μm.
Fig. 5 shows the corresponding normalized output
power as a function of total device width. The output
power shows no clear dependence on frequency, as
expected, but shows a gentle decrease with increasing
width. This decrease in output power at large widths is
because of a decrease in gain and fmax.
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PAE (%)
Total Device Width (μ μm)
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NF = 60
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Fig. 3: fmax as a function of total device width. The numbers
beside each symbol denote the number of fingers in that device.
VDD = 1.1 V, ID = 200 mA/mm.
Fig. 2: PAE and normalized output power as a function of
measurement frequency for single gate and double gate contact
structures.
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Fig. 5: Normalized output power, measured at different
frequencies, versus total device width. Device width is increased
by keeping NF constant at 60 and increasing WF from 0.5 μm to
5 μm.
Fig. 6 shows the peak PAE versus device width for
structures in which WF=1.5 μm and the device width is
increased by increasing the number of fingers from 20 to
120. Similar to Fig. 4, but to a smaller scale, the peak PAE
initially increases with width for W < 100 μm and remains
constant for W > 100 μm. PAE also decreases with
increasing frequency. The change in PAE is mainly due to
the change in the power gain.

Fig. 6: PAE, measured at different frequencies, as a function of
total device width. Device width is increased by keeping WF
constant and increasing NF from 20 to 120.
The corresponding normalized output power is shown
as a function of total device width in Fig. 7. The output
power shows a slight decrease with increasing device width
but is rather independent of frequency. This is further
discussed below.
IV. COMPARISON OF 45 NM AND 65 NM TECHNOLOGIES
We now compare the RF power performance of 45 nm
low-power devices with 65 nm devices. Fig. 8 shows the
de-embedded fmax as a function of device width for both 45
nm and 65 nm technologies. For 45 nm devices, NF=60
and the device width is increased by increasing WF from
0.5 μm to 5 μm (same data as in Fig. 3). For the 65 nm
devices, the device width is increased by connecting
multiple unit cells in parallel. Each unit cell has 12 fingers
of 2 μm finger width. It is clear from Fig. 8 that fmax is
slightly higher for the 45 nm devices with W < 100 μm.
However, at large device widths fmax of 45 nm devices is
lower than 65 nm devices. This is because the finger width
for the 45 nm devices is large (> 3 μm), which results in a
rather high gate resistance and thus reduced fmax. There is
no reason that prevents 45 nm technologies from achieving
higher fmax at large device widths by using optimized
values of WF. This should boost its maximum power
handling ability.
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Fig. 7: Normalized output power, measured at different
frequencies, versus total device width. Device width is increased
by keeping WF constant and increasing NF from 20 to 120.
Fig. 8: fmax as a function of device width for 45 nm and 65 nm
devices. VDD = 1.1 V for 45 nm and VDD = 1 V for 65 nm.
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An alternative way to compare the RF power
performance of 45 and 65 nm technologies is to focus on
PAE and Pout at different frequencies as a function of the
ratio of the application frequency to the fmax of the device.
The higher the f/fmax ratio, the closer the device is operating
to its frequency limit. As the operating frequency
approaches fmax, the power gain decreases, resulting in a
decrease in the peak PAE [8]. Fig. 9 shows peak PAE,
measured at ID=200 mA/mm, as a function of f/fmax for
both 45 nm and 65 nm devices. When viewed this way,
both CMOS technologies behave in a very similar way.
Fig. 10 shows the normalized output power as a
function of f/fmax for 45 nm and 65 nm devices. The output
power is relatively constant across measurement frequency
for both devices. There is also a slightly higher output
power in the 45 nm devices which can be attributed to the
higher VDD (1.1 V for 45 nm versus 1 V for 65 nm).
Hence, we conclude that the RF power performance of
45 nm low-power technology is very similar to that of 65
nm technology. This is not surprising because the gate
lengths for both technologies are close and fmax is already
quite high (> 200 GHz) for 65 nm technology. Most of the
60 GHz applications require a significant amount of digital
content. Our research suggests that designers can take
advantage of the higher integration density of 45 nm
CMOS without losing any of the RF power performance of
65 nm technology.
V. CONCLUSION
We have studied the power and frequency response of
45 nm low-power CMOS devices. Our data shows that the
peak output power density in these devices, at ID=200
mA/mm, is around 140 mW/mm and the peak PAE is over
70%. A device structure with a double gate contact shows a
slight improvement in fmax and Pout compared to a single
gate contact structure. Increasing the device width leads to
a decrease in PAE and Pout due to a decrease in fmax for
large width devices. For a given device width, fmax, PAE
and Pout are independent of the number of fingers and unit
finger width as long as the unit finger width is less than 1.5
μm. Comparison of frequency and power data of 45 nm
and 65 nm devices shows that the RF power potential of 45
nm low-power technology is very similar to that of 65 nm
technology.
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amplifier with 11% PAE in 65nm CMOS”, International
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CMOS”, Radio Frequency Integrated Circuits Symposium,
2008, pp. 641-644.
[3] K. Raczkowski, et al, “50-to-67GHz ESD-Protected Power
Amplifiers in Digital 45nm LP CMOS”, International Solid
State Circuits Conference, 2009, pp. 382 – 384.
[4] E. Cohen, et al, “60GHz 45nm PA for Linear OFDM Signal
with Predistortion Correction achieving 6.1% PAE and -28dB
EVM”, Radio Frequency Integrated Circuits Symposium,
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[5] J. Yuan, et al, “A 45nm low cost low power platform by using
integrated dual-stress-liner technology”, VLSI technology
symposium, 2006, pp. 100-101.
[6] U. Gogineni, et al, “Effect of substrate contact shape and
placement on RF characteristics of 45 nm low-power CMOS
devices”, Radio Frequency Integrated Circuits Symposium,
2009, pp. 163-166.
[7] Z. Luo, et al, “High performance and low power transistors
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[8] J. Scholvin, et al, “Fundamental power and frequency limits
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International Electron Device Meeting, 2006, pp. 217-220.

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Fig. 9: Dependence of peak PAE on the f/fmax ratio for 45 nm and
65 nm devices. ID=200 mA/mm, VDD = 1.1 V for 45 nm, VDD = 1
V for 65 nm.
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Fig. 10: Normalized output power versus f/fmax ratio for 45 nm
and 65 nm devices. ID=200 mA/mm, VDD = 1.1 V for 45 nm,
VDD = 1 V for 65 nm.
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